Synchronization, Re-Synchronization, Addressing, and Serialized Signal Processing for Daisy-Chained Communication Devices

• US 20120243559A1
• Filed: 03/22/2012
• Published: 09/27/2012
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Analog Devices, Inc.
• Inventors: Pan, Yang, Josefsson, Olafur M., Yan, Dongqin, Huin, Camille L. C. J.
• Granted Patent: US 8,731,002 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/1605 Fixed allocated frame structures
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques for use in a data communication system having a number of communicatively coupled device include techniques for synchronization and re-synchronization of frame and bit clocks, techniques for assigning device address, techniques for dynamically controlling transmit power based on the number of devices, and techniques for serialized signal processing.

Claims

1. A time-division multiplexed communication system comprising:

a data line;

a controller including a clock output for providing a clock signal, a frame sync output for providing a frame sync signal indicating the beginning of each of a number of successive frames, and a data pin coupled to the data line; and

at least one slave-only device in communication with the controller, each slave-only device including a clock input coupled to the clock output of the controller for receiving the clock signal, a data pin coupled to the data line, a frame sync input, and a frame sync output, the controller and the at least one slave-only device interconnected in a chain configuration beginning with the controller, wherein the frame sync input of each slave-only device is coupled to the frame sync output of the previous device in the chain, and wherein the controller provides the frame sync signal on its frame sync output, wherein each slave-only device is configured to perform an auto-initialization process including;

monitoring the frame sync input for frame sync signals; and

after receiving at least two frame sync signals on the frame sync input;

generating an inner frame clock based on a plurality of the received frame sync signals, the inner frame clock synchronized with the frame sync signal provided on the controller frame sync output;

outputting the inner frame clock on the frame sync output; and

entering a data passing mode, including generating an internal operational clock based on the inner frame clock.

2. A system according to claim 1, wherein generating the inner frame clock comprises determining the number of clock signal cycles in a frame based on the clock signal and the plurality of frame sync signals, and wherein generating the internal operational clock comprises generating the internal operational clock based on the inner frame clock and the number of clock signal cycles in a frame.

3. A system according to claim 1, wherein the at least one slave-only device comprises a plurality of slave-only devices, and wherein all of the slave-only devices are configured to access the same number of time slots per frame.

4. A system according to claim 1, wherein the at least one slave-only device comprises a plurality of slave-only devices, and wherein at least two slave-only devices are configured to access different numbers of time slots per frame.

5. A system according to claim 1, wherein the at least one slave-only device comprises a plurality of slave-only devices, and wherein all of the slave-only devices are the same type of device.

6. A system according to claim 1, wherein the at least one slave-only device comprises a plurality of slave-only devices, and wherein at least two slave-only devices are different types of devices.

7. A system according to claim 1, wherein each slave-only device is configured to determine a maximum number of slave-only devices supported by the controller based on the clock signal and the frame sync signal.

8. A system according to claim 7, wherein the data pin of each slave-only device includes a programmable driver, and wherein each slave-only device is configured to program a power setting of the programmable driver based on the maximum number of slave-only devices supported by the controller.

9. A system according to claim 1, wherein the data pin of each slave-only device is configured or configurable for at least one of:

transmitting data via the data line;

or

receiving data from the data line.

10. A system according to claim 1, wherein the at least one slave-only device includes at least one digital MEMS microphone device.

11. Apparatus comprising at least one slave-only device for operation in a time-division multiplexed communication system having a controller in communication with the at least one slave-only device, each slave-only device comprising:

a clock input for receiving a clock signal;

a frame sync input for receiving a frame sync signal indicating the start of each of a number of successive frames;

a frame sync output for outputting a delayed frame sync signal; and

a slave-only TDM bus interface coupled to the clock input, the frame sync input, and the frame sync output and including a data pin for coupling to a data line, wherein the TDM bus interface is configured to perform an auto-initialization process including;

monitoring the frame sync input for frame sync signals; and

after receiving at least two frame sync signals on the frame sync input;

generating an inner frame clock based on a plurality of the received frame sync signals, the inner frame clock synchronized with a frame sync signal provided on a controller frame sync output;

outputting the inner frame clock on the frame sync output; and

entering a data passing mode, including generating an internal operational clock based on the inner frame clock.

12. Apparatus according to claim 11, wherein the TDM bus interface is configured to determine the number of clock signal cycles in a frame based on the clock signal and the plurality of frame sync signals, and wherein the TDM bus interface is further configured to generate the internal operational clock based on the inner frame clock and the number of clock signal cycles in a frame.

13. Apparatus according to claim 12, wherein the TDM bus interface is further configured to determine a maximum number of slave-only devices that can be supported in a chain based on the clock signal and the frame sync signal received on the frame sync input.

14. Apparatus according to claim 13, wherein the data pin includes a programmable driver, and wherein the TDM bus interface is further configured to program a power setting of the programmable driver based on the maximum number of slave-only devices.

15. Apparatus according to claim 11, wherein the data pin is configured or configurable for at least one of:

transmitting data via the data line;

or

receiving data from the data line.

16. Apparatus according to claim 11, further comprising a digital MEMS microphone coupled to the slave-only TDM bus interface.

17. Apparatus according to claim 11, wherein the at least one slave-only device comprises a plurality of slave-only devices, and wherein the plurality of slave-only devices are integrated onto a single chip.

18. Apparatus according to claim 17, further comprising the controller integrated with the plurality of slave-only devices onto the single chip.

19. A method for automatically initializing a slave-only device in a time-division multiplexed communication system having a controller in communication with at least one slave-only device, wherein data is transmitted in successive frames, each frame including a predetermined number of time slots, the method comprising:

monitoring, by a TDM interface of the slave-only device, a frame sync input of the slave-only device for frame sync signals; and

after receiving at least two frame sync signals on the frame sync input;

generating an inner frame clock for the slave-only device based on a plurality of the received frame sync signals, the inner frame clock synchronized with a frame sync signal output by the controller;

outputting the inner frame clock on a frame sync output of the slave-only device; and

entering a data passing mode, including generating an internal operational clock for the slave-only device based on the inner frame clock.

20. A method according to claim 19, wherein generating the internal operational clock comprises:

receiving a clock signal from the controller via a clock input of the slave device;

determining the number of clock signal cycles in a frame based on clock signal and the plurality of frame sync signals; and

generating the internal operational clock based on the inner frame clock and the number of clock signal cycles in a frame.

21. A method according to claim 20, further comprising:

determining a maximum number of slave-only devices based on the clock signal and the frame sync signal.

22. A method according to claim 21, wherein the slave-only device includes a programmable driver for the data output, and wherein the method further comprises:

programming the programmable driver based on the maximum number of slave-only devices.

23. A method according to claim 20, wherein the slave-only device includes an analog-to-digital transducer or digital-to-analog transducer, and wherein the method further comprises:

providing the internal frame clock to the transducer.

24. A method according to claim 23, wherein the transducer is a microphone that produces digital audio samples.