Design-Based Inspection Using Repeating Structures

• US 20120243773A1
• Filed: 03/14/2012
• Published: 09/27/2012
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Kulkarni, Ashok V., Chen, Chien-Huei (Adam)
• Granted Patent: US 9,170,211 B2
• Time in Patent Office: Days
• US Class Current: 382/149
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/95607 using a comparative method

Abstract

Systems and methods for design-based inspection using repeating structures are provided.

Claims

1. A computer-implemented method for inspecting a wafer, comprising:

identifying multiple instances of structures in a design for a wafer, wherein the structures have the same or substantially the same geometrical characteristics, and wherein said identifying is performed using design data for the design;

comparing output of an inspection system generated for two or more of the multiple instances formed on the wafer to each other, wherein the two or more of the multiple instances are located within the same die on the wafer; and

detecting defects on the wafer based on results of said comparing, wherein said identifying, said comparing, and said detecting are performed using a computer system.

2. The method of claim 1, wherein said identifying is further performed without using periodicity of the structures.

3. The method of claim 1, wherein said identifying is not performed using output of an inspection system generated for a wafer.

4. The method of claim 1, wherein said identifying is not performed based on cell size of the design.

5. The method of claim 1, wherein the multiple instances do not occur in the design with any periodicity.

6. The method of claim 1, wherein each of the multiple instances comprise only one structure in the design.

7. The method of claim 1, wherein each of the multiple instances comprise multiple structures in the design.

8. The method of claim 1, wherein said identifying comprises identifying multiple instances of the same design cell in the design using a design layout hierarchy for the design.

9. The method of claim 1, wherein said identifying comprises searching the design data for any instances of a known pattern of interest by performing a polygon match of the structures that make up the known pattern of interest and the structures in the design data.

10. The method of claim 1, wherein said identifying comprises performing Fourier analysis of the design data.

11. The method of claim 1, wherein said identifying is further performed using design layer intent for the design data.

12. The method of claim 1, wherein said identifying comprises analyzing a design layout for the design data at a polygonal level to identify the multiple instances of the structures.

13. The method of claim 1, wherein said identifying is performed by identifying a first structure in the design data that can be included in the multiple instances and then iteratively searching the design data for other structures that can also be included in the multiple instances with the first structure.

14. The method of claim 1, wherein the multiple instances comprise at least three instances of the structures.

15. The method of claim 1, wherein the multiple instances comprise all instances of the structures in the design data.

16. The method of claim 1, further comprising prior to said comparing, interpolating the multiple instances of the structures to a common pixel grid.

17. The method of claim 1, further comprising during inspection and prior to said comparing, aligning the output generated for the two or more of the multiple instances in corresponding pixel streams of the output.

18. A non-transitory computer-readable medium storing program instructions executable on a computer system for performing a computer-implemented method for inspecting a wafer, wherein the computer-implemented method comprises:

identifying multiple instances of structures in a design for a wafer, wherein the structures have the same or substantially the same geometrical characteristics, and wherein said identifying is performed using design data for the design;

comparing output of an inspection system generated for two or more of the multiple instances formed on the wafer to each other, wherein the two or more of the multiple instances are located within the same die on the wafer; and

detecting defects on the wafer based on results of said comparing.

19. A system configured to inspect a wafer, comprising:

an inspection subsystem configured to generate output for a wafer; and

a computer subsystem configured for;

identifying multiple instances of structures in a design for the wafer, wherein the structures have the same or substantially the same geometrical characteristics, and wherein said identifying is performed using design data for the design;

comparing output of the inspection subs stem generated for two or more of the multiple instances formed on the wafer to each other, wherein the two or more of the multiple instances are located within the same die on the wafer; and

detecting defects on the wafer based on results of said comparing.