REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING

• US 20120244664A1
• Filed: 06/04/2012
• Published: 09/27/2012
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Jin, Yonggang, Baraton, Xavier, Che, Faxing
• Granted Patent: US 9,012,269 B2
• Time in Patent Office: Days
• US Class Current: 438/118
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

Claims

1. A method, comprising:

packaging an integrated circuit die, the packaging including;

positioning an active surface of the integrated circuit die on a first surface;

positioning an inactive surface of the integrated circuit die in an encapsulant in a mold chamber;

covering all sides of the integrated circuit die with the encapsulant by compressing the first surface towards the encapsulant in the mold chamber; and

preventing the encapsulant from covering the inactive surface and the active surface of the integrated circuit die by compressing the inactive surface of the integrated circuit die into a resilient surface in the mold chamber.

2. The method of claim 1 wherein preventing the encapsulant from covering the inactive surface includes directly contacting the inactive surface of the integrated circuit die with the resilient surface in the mold chamber.

3. The method of claim 2 wherein preventing the encapsulant from covering the inactive surface includes controlling a rate of the compressing.

4. The method of claim 2, further comprising removing the integrated circuit die from the molding chamber and removing the first surface from the integrated circuit die, a height of the encapsulant being equal to a height of an integrated circuit die.

5. The method of claim 4, further comprising coupling a redistribution layer to a bond pad of the integrated circuit die.

6. The method of claim 1 wherein the first surface is adhesive.

7. A method, comprising:

providing a molding chamber, the molding chamber having an interior surface;

forming an encapsulant around sides of an integrated circuit die in the molding chamber;

compressing an inactive surface of the integrated circuit die into a resilient surface on the interior surface of the molding chamber by providing pressure to a support plate that is attached to an active surface of the integrated circuit die, the resilient surface including a first portion and a second portion, the first portion being spaced from the second portion by a first distance, the inactive surface of the integrated circuit being spaced from the active surface by a second distance that is substantially equal to the first distance.

8. The method of claim 7 wherein forming the encapsulant including providing the encapsulant before compressing the inactive surface into the resilient surface.

9. The method of claim 8 wherein forming the encapsulant around the sides of the integrated circuit die includes maintaining the encapsulant in a liquid state by controlling a temperature of the encapsulant in the molding chamber.

10. The method of claim 9 wherein the inactive surface of the integrated circuit die directly contacts the first portion of the resilient surface.

11. The method of claim 7 wherein forming the encapsulant includes providing the encapsulant occurs after the inactive surface of the integrated circuit is brought into contact with the resilient surface of the molding chamber.

12. A method of forming an encapsulation layer for fan-out wafer level packaging, comprising:

positioning a first surface of an integrated circuit on a carrier; and

compressing the integrated circuit into a molding chamber having an encapsulant therein, the molding chamber sized and shaped to allow a second surface of the integrated circuit to contact a bottom surface of the molding chamber.

13. The method of claim 12 wherein the integrated circuit is compressed into the molding chamber by applying a force to a surface of the carrier not in contact with the integrated circuit.

14. The method of claim 12 wherein the bottom surface of the molding chamber is covered with a protective layer to prevent damage to the integrated circuit.

15. The method of claim 12 wherein the carrier includes an adhesive layer and a support layer, the integrated circuit separated from the support layer by the adhesive layer.

16. The method of claim 12 wherein a height of the encapsulant is substantially equal to a height of the integrated circuit.