METHODS OF FABRICATING SEMICONDUCTOR DEVICES

• US 20120244670A1
• Filed: 03/19/2012
• Published: 09/27/2012
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Hajin, Do, Jinho, Kim, WeonHong, Hong, Kyungil, Song, Moonkyun
• Granted Patent: US 8,778,753 B2
• Time in Patent Office: Days
• US Class Current: 438/229
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/2822 with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

preparing a substrate including an NMOS transistor region and a PMOS transistor region;

forming a silicon-germanium layer on the PMOS transistor region;

injecting nitrogen atoms in an upper portion of the silicon-germanium layer; and

forming a first gate dielectric layer on the NMOS transistor region and the PMOS transistor region after the injecting the nitrogen atoms.

2. The method of claim 1, further comprising:

heat treating the first gate dielectric layer; and

forming a gate electrode pattern on the first gate dielectric layer such that the silicon-germanium layer is exposed.

3. The method of claim 2, wherein the heat treating the first gate dielectric layer is performed before the forming the gate electrode pattern.

4. The method of claim 2, further comprising:

forming a source region and a drain region in the silicon-germanium layer exposed by the gate electrode pattern.

5. The method of claim 2, further comprising:

etching the silicon-germanium layer exposed by the gate electrode pattern to form a recessed region in the PMOS transistor region; and

forming a compressive stress pattern in the recessed region, the compressive stress pattern including a silicon-germanium material.

6. The method of claim 1, further comprising:

forming a silicon capping layer on the silicon-germanium layer before the forming the first gate dielectric layer.

7. The method of claim 6, wherein the forming the first gate dielectric layer includes thermally oxidizing the silicon capping layer.

8. The method of claim 7, wherein the injecting the nitrogen atoms is performed before the forming the silicon capping layer.

9. The method of claim 1, wherein the nitrogen atoms are injected into an upper portion of the silicon-germanium layer in the PMOS transistor region, and an upper portion of the substrate in the NMOS transistor region.

10. The method of claim 1, wherein the nitrogen atoms are injected to a depth below 10% of the thickness of the silicon-germanium layer from a top surface of the silicon-germanium layer.

11. The method of claim 1, wherein the nitrogen atoms are injected into an upper portion of the silicon-germanium layer such that the silicon-germanium layer has a nitrogen concentration of about 5×

10¹⁰ to about 2×

10¹⁶ atm/cm³.

12. A method of fabricating a semiconductor device, the method comprising:

preparing a substrate including a first region and a second region;

forming a silicon-germanium layer on the first region and the second region;

forming a nitrogen impurity region in an upper portion of the silicon-germanium layer;

forming a first gate dielectric layer on the nitrogen impurity region;

removing the first gate dielectric layer in the second region; and

forming a second gate dielectric layer on the first region and the second region.

13. The method of claim 12, further comprising:

heat treating the first gate dielectric layer,

wherein the nitrogen impurity region is formed before the heat treating the first gate dielectric layer.

14. The method of claim 12, wherein the second gate dielectric layer includes a high-k dielectric layer having a higher dielectric constant than that of a silicon oxide layer.

15. The method of claim 14, further comprising:

forming a third gate dielectric layer between the first gate dielectric layer and the second gate dielectric layer,

wherein the third gate dielectric layer includes a silicon oxynitride layer.

16. A method of manufacturing a semiconductor device, the method comprising:

forming a silicon-germanium layer on one of first and second regions of a substrate;

forming a nitrogen impurity region in an upper portion of the silicon-germanium layer; and

forming at least one gate dielectric layer on the nitrogen impurity region.

17. The method of claim 16, wherein the nitrogen impurity region is formed to a depth below 10% of the thickness of the silicon-germanium layer from a top surface of the silicon-germanium layer.

18. The method of claim 16, wherein the nitrogen impurity region has a nitrogen concentration of about 5×

10¹⁰ to about 2×

10¹⁶ atm/cm³.

19. The method of claim 16, wherein the at least one gate dielectric layer includes at least one of hafnium, tantalum, and silicon.

20. The method of claim 16, wherein the at least one gate dielectric layer includes first, second and third gate dielectric layers, and the second and third gate dielectric layers are thinner than the first gate dielectric layer.