METHOD OF MANUFACTURING A BASE SUBSTRATE FOR A SEMI-CONDUCTOR ON INSULATOR TYPE SUBSTRATE

• US 20120244687A1
• Filed: 03/21/2012
• Published: 09/27/2012
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Kononchuk, Oleg, Allibert, Frederic
• Granted Patent: US 8,765,571 B2
• Time in Patent Office: Days
• US Class Current: 438/479
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02301 in-situ cleaning
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76262 using selective deposition of single crystal silicon, i.e. SEG techniques

Abstract

A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.

Claims

1. A method of manufacturing a base substrate, which comprises:

(a) providing a silicon substrate having an electrical resistivity above 500 Ohm·

cm,

(b) cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof,

(c) providing, on the silicon substrate, a layer of dielectric material, and

(d) providing, on the layer of dielectric material, a layer of poly-crystalline silicon,

wherein steps (b), (c) and (d) are implemented successively in an enclosure.

2. The method according to claim 1, wherein the cleaning comprises a heat treatment in a reducing atmosphere.

3. The method according to claim 1, wherein the dielectric material comprises silicon oxide.

4. The method according to claim 3, wherein the providing of the layer of dielectric material comprises conducting a heat treatment of the silicon substrate in an oxidizing atmosphere to form the layer.

5. The method according to claim 4, wherein the oxidizing atmosphere comprises an inert gas having between 100 and 5000 ppm oxygen.

6. The method according to one of claim 1, wherein the layer of poly-crystalline silicon comprises is deposited at a temperature of less than or equal to 900°

C.

7. The method according to claim 1, wherein the enclosure comprises an epitaxy frame.

8. The method according to claim 1, wherein the enclosure comprises a first chamber for cleaning the silicon substrate, a second chamber for providing the layer of dielectric material and a third chamber for providing the layer of poly-crystalline silicon, the chambers being connected via airlocks isolated from an exterior.

9. A method for the manufacture of a semi-conductor on insulator type substrate method which comprises transferring onto the base substrate according to claim 1 a layer of insulating material and a useful layer of semiconductor material to form the semi-conductor on insulator type substrate.

16. In a method of manufacturing a semi-conductor on insulator type substrate, the improvement which comprises using as a receiver substrate the base substrate manufactured according to claim 1.

10. A method for avoiding contamination when providing a high frequency base substrate, which comprises providing an enclosure for preparation of the substrate therein, wherein the substrate is prepared by conducting successively the following steps in the enclosure:

(a) providing a silicon substrate having an electrical resistivity above 500 Ohm·

cm,

(b) cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof,

(c) providing, on the silicon substrate, a layer of dielectric material, and

(d) providing, on the layer of dielectric material, a layer of poly-crystalline silicon to form the base substrate.

11. The method according to claim 10, wherein the enclosure comprises a first chamber for cleaning the silicon substrate, a second chamber for providing the layer of dielectric material and a third chamber for providing the layer of poly-crystalline silicon, the chambers being connected via airlocks isolated from an exterior.

12. A system for manufacturing a base substrate for use during manufacture of a semi-conductor on insulator type substrate, comprising an enclosure in which a silicon substrate having an electrical resistivity above 500 Ohm·

cm is provided;

wherein the silicon substrate is cleaned in the enclosure so as to remove native oxide and dopants from a surface thereof;

wherein a layer of dielectric material us subsequently formed on the silicon substrate; and

wherein a layer of poly-crystalline silicon is formed on the dielectric material.

13. The system according to claim 12, wherein the enclosure comprises a first chamber in which the silicon substrate is cleaned, a second chamber in which the layer of dielectric material is formed and a third chamber in which the layer of poly-crystalline silicon is formed, the chambers being connected via airlocks isolated from an exterior.

14. The system according to claim 12, comprising:

means for accessing the enclosure for introducing or extracting substrates therefrom,

means for closing the enclosure to shut off the access means in a sealed manner,

means for supporting the substrate during cleaning or formation of layers thereon, and

means for heating the enclosure.

15. The system according to claim 14, which further comprises:

means for introducing gases or reagents of suitable composition for conducting the various steps for manufacturing the base substrate, and

means for extracting residual gases or reagents after each step is conducted.

17. In a method of manufacturing a semi-conductor on insulator type substrate, the improvement which comprises manufacturing as a receiver substrate a high resistivity base substrate in the system according to claim 12.