METHOD FOR PATTERNING A FULL METAL GATE STRUCTURE
First Claim
1. A method of patterning a gate structure on a substrate, comprising:
- preparing a metal gate structure on a substrate, said metal gate structure including a high dielectric constant (high-k) layer, a first gate layer formed on said high-k layer, and a second gate layer formed on said first gate layer, said first gate layer comprising one or more metal-containing layers;
preparing a mask layer with a pattern overlying said metal gate structure;
transferring said pattern to said second gate layer;
transferring said pattern to said first gate layer;
transferring said pattern in said first gate layer to said high-k layer; and
prior to said transferring said pattern to said high-k layer, passivating an exposed surface of said first gate layer using a nitrogen-containing and/or carbon-containing environment to reduce under-cutting of said first gate layer relative to said second gate layer,wherein said passivating is performed separately from or in addition to said transferring said pattern to said first gate layer.
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Abstract
A method of patterning a gate structure on a substrate is described. The method includes preparing a metal gate structure on a substrate, wherein the metal gate structure includes a high dielectric constant (high-k) layer, a first gate layer formed on the high-k layer, and a second gate layer formed on the first gate layer, and wherein the first gate layer comprises one or more metal-containing layers. The method further includes preparing a mask layer with a pattern overlying the metal gate structure, transferring the pattern to the second gate layer, transferring the pattern to the first gate layer, and transferring the pattern in the first gate layer to the high-k layer, and prior to the transferring of the pattern to the high-k layer, passivating an exposed surface of the first gate layer using a nitrogen-containing and/or carbon-containing environment to reduce under-cutting of the first gate layer relative to the second gate layer, wherein the passivating is performed separately from or in addition to the transferring of the pattern to the first gate layer.
27 Citations
20 Claims
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1. A method of patterning a gate structure on a substrate, comprising:
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preparing a metal gate structure on a substrate, said metal gate structure including a high dielectric constant (high-k) layer, a first gate layer formed on said high-k layer, and a second gate layer formed on said first gate layer, said first gate layer comprising one or more metal-containing layers; preparing a mask layer with a pattern overlying said metal gate structure; transferring said pattern to said second gate layer; transferring said pattern to said first gate layer; transferring said pattern in said first gate layer to said high-k layer; and prior to said transferring said pattern to said high-k layer, passivating an exposed surface of said first gate layer using a nitrogen-containing and/or carbon-containing environment to reduce under-cutting of said first gate layer relative to said second gate layer, wherein said passivating is performed separately from or in addition to said transferring said pattern to said first gate layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of patterning a gate structure on a substrate, comprising:
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preparing a metal gate structure on a substrate, said metal gate structure including a high-k layer, a metal alloy layer formed on said high-k layer, and a gate layer formed on said metal alloy layer, said metal alloy layer comprising an aluminum-alloy and/or titanium-alloy; preparing a mask layer with a pattern overlying said metal gate structure; transferring said pattern to said gate layer; transferring said pattern to said metal alloy layer; transferring said pattern in said metal alloy layer to said high-k layer; and passivating an exposed surface of said metal alloy layer using a nitrogen-containing environment and/or carbon-containing environment to reduce under-cutting of said metal alloy layer relative to said gate layer.
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Specification