TECHNIQUES FOR DIFFERENT MEMORY DEPTHS ON DIFFERENT PARTITIONS

• US 20120246379A1
• Filed: 03/25/2011
• Published: 09/27/2012
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kelleher, Brian, Kilgariff, Emmett
• Granted Patent: US 9,477,597 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

Embodiments of the present technology are directed toward techniques for enabling different memory partitions to have different memory depths.

Claims

1. A method comprising:

disabling one or more of a plurality of memory interfaces and enabling the other of the plurality of memory interfaces of a computing device;

coupling one or more memory devices to each of the enabled memory interfaces and one or more additional memory devices to a subset of the enabled memory devices, wherein a first depth of memory is coupled to one or more memory interfaces and a second depth of memory is coupled to one or more other memory interfaces; and

mapping each of a plurality of physical address ranges to a corresponding memory interface and a memory space of a corresponding memory device, wherein the physical address ranges of the additional memory devices includes a given offset.

2. The method according to claim 1, wherein the given offset is beyond the memory space of the set of one or more memory devices coupled across the set of enabled memory interfaces.

3. The method according to claim 1, wherein the memory width of the set of one or more memory devices coupled across the set of enable memory interfaces is a non-power of two.

4. The method according to claim 1, wherein the computing device comprises a graphics processing unit.

5. The method according to claim 4, wherein the plurality of memory interfaces comprise frame buffer memory interfaces.

6. The method according to claim 1, wherein the one or more disabled memory interfaces include a manufacturing defect.

7. A method comprising:

receiving a memory access request at a given physical address;

determining a given memory interface and a given location in a corresponding memory device for the given physical address from a mapping of a plurality of physical address ranges to corresponding memory interfaces and the memory space of a memory device of the corresponding memory interfaces, wherein the physical address range of one or more additional memory devices coupled to a subset of enabled memory devices include a given offset; and

accessing, using the given memory interface, the given location in the corresponding memory device.

8. The method according to claim 7, wherein the given offset is beyond the memory space of a set of one or more memory devices coupled across the set of enabled memory interfaces.

9. The method according to claim 7, wherein the memory width of the set of one or more memory devices coupled across the set of enabled memory interfaces is a non-power of two.

10. The method according to claim 7, wherein the computing device comprises a graphics processing unit.

11. The method according to claim 10, wherein the plurality of memory interfaces comprise frame buffer memory interfaces.

12. A method comprising:

an initialization phase including;

disabling one or more of a plurality of memory interfaces and enabling the other of the plurality of memory interfaces of a computing device;

coupling one or more memory device to each of the enabled memory interfaces and one or more additional memory devices to a subset of the enabled memory devices, wherein a first depth of memory is coupled to one or more memory interfaces and a second depth of memory is coupled to one or more other memory interfaces; and

mapping each of a plurality of physical address ranges to a corresponding memory interface and a memory space of a corresponding memory device, wherein the physical address ranges of the additional memory devices includes a given offset; and

an operating phase including;

receiving a memory access request at a given physical address;

determining a given memory interface and a given location in a corresponding memory device for the given physical address from the mapping of each of a plurality of physical address ranges to a corresponding memory interface and a memory space of a corresponding memory device, wherein the physical address ranges of the additional memory devices includes a given offset; and

accessing, using the given memory interface, the given location in the corresponding memory device.

13. The method according to claim 12, wherein the given offset is beyond the memory space of the set of one or more memory devices coupled across the set of enabled memory interfaces.

14. The method according to claim 12, wherein the memory width of the set of one or more memory devices coupled across the set of enable memory interfaces is a non-power of two.

15. The method according to claim 12, wherein the computing device comprises a graphics processing unit.

17. The method according to claim 12, wherein the one or more disabled memory interfaces include a manufacturing defect.

18. The method according to claim 12, wherein the memory access request is received by a memory controller.

19. The method according to claim 18, wherein the memory controller determines the given memory interface and the given location in the corresponding memory device for the given physical address from the mapping.

20. The method according to claim 12, wherein initialization phase is performed by a manufacturer of the computing device.

16. The method according to claim 16, wherein the plurality of memory interfaces comprise frame buffer memory interfaces.