NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING

• US 20120246380A1
• Filed: 10/06/2010
• Published: 09/27/2012
• Est. Priority Date: 10/21/2009
• Status: Abandoned Application

• Current Assignee: GSI Technology Incorporated
• Original Assignee: GSI Technology Incorporated
• Inventors: Akerib, Avidan, Ehrman, Eli, Agam, Oren, Meyassed, Moshe, Meir, Yehoshua, Fukuzo, Yukio
• Application Number:
  US13/502,797
• Publication Number:
  US 20120246380A1
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.

Claims

1. A memory device comprising:

an external device interface connectable to an external device communicating with said memory device;

an internal processing element to process data stored on said device; and

multiple banks of storage, wherein each bank comprises a plurality of storage units and each storage unit having two ports, an external port connectable to said external device interface and an internal port connected to said internal processing element.

2. The memory device according to claim 1 wherein said plurality of storage units are formed into an upper row of units and a lower row of units and also comprising a computation belt between said upper and lower rows, wherein said internal port and said processing element are located within said computation belt.

3. The memory device according to claim 2 and wherein said computation belt comprises an internal bus to transfer said data from said internal port to said processing element.

4. The memory device according to claim 3 wherein said internal bus is a reordering bus to reorder the output of said internal port to match a pre-storage logical order of said data.

5. The memory device according to claim 4 and wherein said reordering bus comprises four lines each to provide bytes from one of said internal ports to every fourth byte storage unit of said processing element.

6. The memory device according to claim 5 and wherein each said line connects between one internal port and said processing element.

7. The memory device according to claim 5 and wherein two of said lines connect between one internal port and said processing element.

8. The memory device according to claim 3 wherein said internal port comprises a plurality of sense amplifiers and a buffer to store the output of said sense amplifiers.

9. The memory device according to claim 1 and wherein said banks of storage comprise one of the following types of memory:

DRAM memory, 3T DRAM, SRAM memory, ZRAM memory and Flash memory.

10. The memory device according to claim 1 and wherein said processing element comprises 3T DRAM elements.

11. The memory device according to claim 10 wherein said processing element also comprises sensing circuitry to sense a boolean function of at least two activated rows of said 3T DRAM elements.

12. The memory device according to claim 1 and wherein said processing element comprises a shift operator.

13. A memory device comprising:

a plurality of storage banks in which to store data formed into an upper row of units and a lower row of units; and

a computation belt between said upper and lower rows to perform on-chip processing of data from said storage units.

14. The memory device according to claim 13 wherein each said bank comprises a plurality of storage units and each storage unit has an internal port forming part of said computation belt.

15. The memory device according to claim 14 and wherein said computation belt additionally comprises a processing element.

16. The memory device according to claim 15 and wherein said computation belt comprises an internal bus to transfer said data from said internal ports to said processing element.

17. The memory device according to claim 16 wherein said internal bus is a reordering bus to reorder the output of said internal port to match a pre-storage logical order of said data.

18. The memory device according to claim 17 and wherein said reordering bus comprises four lines each to provide bytes from one of said internal ports to every fourth byte storage unit of said processing element.

19. The memory device according to claim 18 and wherein each said line connects between one internal port and said processing element.

20. The memory device according to claim 18 and wherein two of said lines connect between one internal port and said processing element.

21. The memory device according to claim 16 wherein said internal port comprises a plurality of sense amplifiers and a buffer to store the output of said sense amplifiers.

22. The memory device according to claim 13 and wherein said banks comprise one of the following types of memory:

DRAM memory, 3T DRAM, SRAM memory, ZRAM memory and Flash memory.

23. The memory device according to claim 15 and wherein said processing element comprises 3T DRAM elements.

24. The memory device according to claim 23 wherein said processing element also comprises sensing circuitry to sense a boolean function of at least two activated rows of said 3T DRAM elements.

25. The memory device according to claim 15 and wherein said processing element comprises a shift operator.

26. A memory device comprising:

a plurality of storage units in which to store data of a bank, wherein said data has a logical order prior to storage and a physical order different than said logical order within said plurality of storage units; and

a within-device reordering unit to reorder said data of a bank into said logical order prior to performing on-chip processing.

27. The memory device according to claim 26 and wherein said storage units are formed of DRAM memory units.

28. The memory device according to claim 26 wherein said reordering unit comprises:

a plurality of sense amplifiers, each to read data of its associated storage unit; and

a data transfer unit to reorder the output of said sense amplifiers to match said logical order of said data.

29. The memory device according to claim 28 wherein N storage units spread across said memory device form a bank to which an external device writes data and wherein said data transfer unit operates to provide data of one bank to an on-chip processing element.

30. The memory device according to claim 29 wherein said data transfer unit comprises an internal bus and at least one compute engine controller at least to indicate to said internal bus how to place data from each of said plurality of said sense amplifiers associated with storage units of one of said banks into said processing element.

31. The memory device according to claim 30 and wherein said internal bus comprises N lines each to transfer a unit of data between said sense amplifiers of one storage unit and every Nth data location of said processing element, wherein said lines together connect to all data locations of said processing element.

32. The memory device according to claim 30 and wherein said internal bus comprises N lines each to transfer a unit of data between said sense amplifiers and every Nth data location of said processing element, wherein two of said lines transfer from one storage unit and two of said lines transfer from a second storage unit.

33. The memory device according to claim 30 wherein said at least one compute engine controller indicates to said internal bus where to begin placement or removal of said data.

34. The memory device according to claim 29 and wherein said processing element comprises a 3T DRAM array, sensing circuitry for sensing the output when multiple rows of said 3T DRAM array are generally simultaneously activated and a write unit to write said output back to said 3T DRAM array.

35. The memory device according to claim 27 and wherein said memory device comprises a 3T DRAM array and said reordering unit writes back to said 3T DRAM array for processing.

36. The memory device according to claim 29 and wherein said processing element comprises a shift operator.

37. The memory device according to claim 34 and wherein said processing element comprises a shift operator.

38. A method of performing parallel processing on a memory device, the method comprising:

on said device, performing neighborhood operations on data stored in a plurality of storage units of a bank, even though said data has a logical order prior to storage and a physical order different than said logical order within said plurality of storage units.

39. The method according to claim 38 and wherein said performing comprises:

accessing data from said plurality of storage units;

reordering said data into its logical order; and

performing neighborhood operations on said reordered data.

40. The method according to claim 38 and wherein said neighborhood operations form part of image processing operations.