Input Output Memory Management Unit (IOMMU) Two-Layer Addressing

• US 20120246381A1
• Filed: 12/02/2011
• Published: 09/27/2012
• Est. Priority Date: 12/14/2010
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc., ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Hummel, Mark, Cheng, Jeffrey, Kegel, Andy, Glaser, Steve, Asaro, Tony, NG, Philip
• Application Number:
  US13/309,750
• Publication Number:
  US 20120246381A1
• Time in Patent Office: Days
• US Class Current: 711/6
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine
• CPC Class Codes: G06F 2212/651 Multi-level translation tables

Abstract

Embodiments of the present invention provide methods, systems, and computer readable media for input output memory management unit (IOMMU) two-layer addressing in the context of memory address translations for I/O devices. According to an embodiment, a method includes translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a guest address translation table according to a process address space identifier associated with an address translation transaction associated with an I/O device, and translating the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.

Claims

1. A method, comprising:

translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a process address space identifier associated with an address translation transaction associated with an I/O device; and

translating the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.

2. The method of claim 1, further comprising:

cascading a plurality of GPA-to-SPA translations for each GVA-to-GPA translation.

3. The method of claim 1, wherein, for a guest page table of a given level, the GVA is operable to index that guest page table to access a guest page table entry associated with a guest root page table pointer that points to a root of a guest page table at a next level.

4. The method of claim 3, further comprising:

translating the guest page table entry to the guest root page table pointer using a GPA-to-SPA translation.

5. The method of claim 4, wherein for a nested page table of a given level, the GPA is operable to index that nested page table to access a nested page table entry associated with a nested root page table pointer that points to a root of a nested page table at a next level.

6. The method of claim 5, wherein the nested page table entry is a SPA.

7. The method of claim 1, wherein:

the translating the GVA further comprises accessing a guest pointer of a device table entry; and

the translating the GPA further comprises accessing a system pointer of the device table entry.

8. The method of claim 1, wherein:

the translating the GVA is manageable by a guest operating system (OS); and

the translating the GPA is manageable by a hypervisor.

9. A system, comprising:

an input/output memory management unit (IOMMU) operable to translate a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a process address space identifier associated with an address translation transaction associated with an I/O device; and

the IOMMU is further operable to translate the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.

10. The system of claim 9, further comprising:

a module operable to cascade a plurality of GPA-to-SPA translations for each GVA-to-GPA translation.

11. The system of claim 9, wherein, for a guest page table of a given level, the GVA is operable to index that guest page table to access a guest page table entry associated with a guest root page table pointer that points to a root of a guest page table at a next level.

12. The system of claim 11, further comprising:

a module operable to translate the guest page table entry to the guest root page table pointer using a GPA-to-SPA translation.

13. The system of claim 12, wherein for a nested page table of a given level, the GPA is operable to index that nested page table to access a nested page table entry associated with a nested root page table pointer that points to a root of a nested page table at a next level.

14. The system of claim 13, wherein the nested page table entry is a SPA.

15. The system of claim 9, wherein:

the IOMMU is further operable to translate the GVA by accessing a guest pointer of a device table entry; and

the IOMMU is further operable to translate the GPA by accessing a system pointer of the device table entry.

16. The system of claim 9, wherein:

a guest operating system (OS) manages the GVA translating; and

a hypervisor manages the GPA translating.

17. A computer readable medium storing instructions, wherein said instructions when executed cause a method comprising:

translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) based on a process address space identifier associated with an address translation transaction associated with an I/O device; and

translating the GPA to a corresponding system physical address (SPA) based on a device identifier associated with the address translation transaction.

18. The computer readable medium of claim 17, wherein:

a guest operating system (OS) manages the GVA translating; and

a hypervisor manages the GPA translating.