STORAGE SYSTEM EXPORTING INTERNAL STORAGE RULES

• US 20120246435A1
• Filed: 03/14/2012
• Published: 09/27/2012
• Est. Priority Date: 03/21/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Meir, Avraham, Anholt, Micha, Maislos, Ariel, Gilyadov, Camuel, Fischer, Doron
• Granted Patent: US 9,021,215 B2
• Time in Patent Office: Days
• US Class Current: 711/169
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage method includes, in a memory controller that accepts memory access commands from a host for execution in one or more memory units, holding a definition of a policy to be applied by the memory controller in the execution of the memory access commands in the memory units. The policy is reported from the memory controller to the host so as to cause the host to format memory access commands based on the reported policy.

Claims

1. A data storage method, comprising:

in a memory controller that accepts memory access commands from a host for execution in one or more memory units, holding a definition of a policy to be applied by the memory controller in the execution of the memory access commands in the memory units; and

reporting the policy from the memory controller to the host so as to cause the host to format memory access commands based on the reported policy.

2. The method according to claim 1, wherein reporting the policy comprises reporting one or more parallelism rules that specify distribution of the memory access commands among the memory units.

3. The method according to claim 1, wherein reporting the policy comprises reporting one or more parallelism rules that specify ranges of logical addresses that are accessed in parallel by the memory controller.

4. The method according to claim 1, wherein reporting the policy comprises reporting one or more pipeline rules that specify properties of an execution pipeline in the memory controller, which executes the memory access commands in the memory units.

5. The method according to claim 1, wherein reporting the policy comprises reporting one or more prioritization rules that specify priorities according to which the memory controller executes the memory access commands in the memory units.

6. The method according to claim 1, wherein reporting the policy comprises reporting one or more redundancy rules that specify a redundant storage scheme applied by the memory controller in the memory units.

7. The method according to claim 1, wherein reporting the policy comprises reporting one or more power consumption rules that specify power consumption characteristics of the memory units.

8. The method according to claim 1, wherein reporting the policy comprises reporting one or more performance rules that specify performance characteristics of individual ones of the memory units.

9. The method according to claim 1, wherein reporting the policy comprises reporting a mapping, defined in the memory controller, between logical addresses associated with the memory access commands and respective physical storage locations in the memory units.

10. The method according to claim 1, wherein reporting the policy comprises reporting to the host that a given rule in the policy is configurable.

11. The method according to claim 1, and comprising:

formatting the memory access commands in the host in accordance with a criterion that optimizes a performance measure of the execution responsively to the reported policy, and sending the formatted memory access commands from the host to the memory controller; and

receiving the memory access commands in the memory controller and executing the received memory access commands in the memory units.

12. The method according to claim 11, wherein the criterion maximizes a throughput of the execution.

13. The method according to claim 11, wherein the criterion minimizes a latency of the execution.

14. The method according to claim 11, wherein the criterion minimizes a power consumption of the execution.

15. The method according to claim 11, wherein reporting the policy comprises reporting a mapping, defined in the memory controller, between logical addresses associated with the memory access commands and respective physical storage locations in the memory units, and wherein formatting the memory access commands comprises assigning the logical addresses to the memory access commands responsively to the reported policy.

16. The method according to claim 11, wherein formatting the memory access commands comprises setting an order of the memory access commands responsively to the reported policy.

17. The method according to claim 11, wherein reporting the policy comprises reporting to the host that a given rule in the policy is configurable, and wherein formatting the memory access commands comprises modifying the given rule in the memory controller by the host.

18. A data storage method, comprising:

holding in a memory controller a definition of a policy to be applied by the memory controller in accessing one or more memory units;

reporting the policy from the memory controller to a host that is coupled to the memory controller; and

in response to reporting the policy, receiving in the memory controller memory access commands that have been formatted by the host in accordance with a criterion that optimizes a performance measure of the execution responsively to the reported policy, and executing the received memory access commands in the memory units.

19. A data storage method, comprising:

receiving from a memory controller a communication to a host reporting a definition of a policy to be applied by the memory controller in accessing one or more memory units;

formatting memory access commands in the host in accordance with a criterion that optimizes a performance measure of the execution responsively to the reported policy; and

sending the formatted memory access commands from the host to the memory controller for execution.

20. A memory controller, comprising:

a memory, which is configured to hold a definition of a policy to be applied by the memory controller in accessing one or more memory units; and

a processor, which is configured to report the policy to a host that is coupled to the memory controller, and, in response to reporting the policy, to receive memory access commands that have been formatted by the host in accordance with a criterion that optimizes a performance measure of the execution responsively to the reported policy, and to execute the received memory access commands in the memory units.

21. The memory controller according to claim 20, wherein the processor is configured to report to the host one or more parallelism rules that specify distribution of the memory access commands among the memory units.

22. The memory controller according to claim 20, wherein the processor is configured to report to the host one or more parallelism rules that specify ranges of logical addresses that are accessed in parallel by the processor.

23. The memory controller according to claim 20, wherein the processor is configured to report to the host one or more pipeline rules that specify properties of an execution pipeline in the processor, which executes the memory access commands in the memory units.

24. The memory controller according to claim 20, wherein the processor is configured to report to the host one or more prioritization rules that specify priorities according to which the processor executes the memory access commands in the memory units.

25. The memory controller according to claim 20, wherein the processor is configured to report to the host one or more redundancy rules that specify a redundant storage scheme applied by the processor in the memory units.

26. The memory controller according to claim 20, wherein the processor is configured to report to the host one or more power consumption rules that specify power consumption characteristics of the memory units.

27. The memory controller according to claim 20, wherein the processor is configured to report to the host one or more performance rules that specify performance characteristics of individual ones of the memory units.

28. The memory controller according to claim 20, wherein the processor is configured to report to the host a mapping, defined in the processor, between logical addresses associated with the memory access commands and respective physical storage locations in the memory units.

29. The memory controller according to claim 20, wherein the processor is configured to report to the host that a given rule in the policy is configurable.

30. A system, comprising:

a memory controller, which is configured to accept memory access commands for execution in one or more memory units, to hold a definition of a policy to be applied in the execution of the memory access commands in the memory units, and to report the policy over an interface; and

a host, which is configured to accept the reported policy from the memory controller over the interface, to format the memory access commands in accordance with a criterion that optimizes a performance measure of the execution responsively to the reported policy, and to send the formatted memory access commands to the memory controller for the execution in the memory units.

31. The system according to claim 30, wherein the criterion maximizes a throughput of the execution.

32. The system according to claim 30, wherein the criterion minimizes a latency of the execution.

33. The system according to claim 30, wherein the criterion minimizes a power consumption of the execution.

34. The system according to claim 30, wherein the memory controller is configured to report to the host a mapping, defined in the memory controller, between logical addresses associated with the memory access commands and respective physical storage locations in the memory units, and wherein the host is configured to assign the logical addresses to the memory access commands responsively to the reported policy.

35. The system according to claim 30, wherein the host is configured to set an order of the memory access commands responsively to the reported policy.

36. The system according to claim 30, wherein the memory controller is configured to report to the host that a given rule in the policy is configurable, and wherein the host is configured to modify the given rule in the memory controller.

37. A host, comprising:

an interface, which is configured to receive from a memory controller a communication reporting a definition of a policy to be applied by the memory controller in accessing one or more memory units; and

a processor, which is configured to format memory access commands in accordance with a criterion that optimizes a performance measure of the execution responsively to the reported policy, and to send the formatted memory access commands over the interface to the memory controller for execution.