Integrated Circuit Semiconductor Devices Including Channel Trenches And Related Methods Of Manufacturing
First Claim
1. A semiconductor memory device comprising:
- a semiconductor substrate including cell array regions and a core region between the cell array regions;
a plurality of phase-change memory cells in each of the cell array regions; and
cell driving transistors in the core region configured to drive the phase-change memory cells, wherein each of the cell driving transistors comprises,first and second spaced apart source/drain regions in the semiconductor substrate,a semiconductor channel region between the first and second source/drain regions, wherein the semiconductor channel region includes a plurality of channel trenches therein,a gate insulating layer on the semiconductor channel region including the plurality of channel trenches, anda gate electrode on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches.
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Abstract
An integrated circuit device may include a semiconductor substrate including an active region and a transistor in the active region. The transistor may include first and second spaced apart source/drain regions in the active region of the semiconductor substrate, and a semiconductor channel region between the first and second source/drain regions. The semiconductor channel region may include a plurality of channel trenches therein between the first and second source/drain regions. A gate insulating layer may be provided on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode may be provided on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. Related methods are also discussed.
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Citations
20 Claims
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1. A semiconductor memory device comprising:
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a semiconductor substrate including cell array regions and a core region between the cell array regions; a plurality of phase-change memory cells in each of the cell array regions; and cell driving transistors in the core region configured to drive the phase-change memory cells, wherein each of the cell driving transistors comprises, first and second spaced apart source/drain regions in the semiconductor substrate, a semiconductor channel region between the first and second source/drain regions, wherein the semiconductor channel region includes a plurality of channel trenches therein, a gate insulating layer on the semiconductor channel region including the plurality of channel trenches, and a gate electrode on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11-15. -15. (canceled)
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16. An integrated circuit device comprising:
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a semiconductor substrate including an active region; a transistor in the active region wherein the transistor includes, first and second spaced apart source/drain regions in the active region of the semiconductor substrate, a semiconductor channel region between the first and second source/drain regions, wherein the semiconductor channel region includes a plurality of channel trenches therein between the first and second source/drain regions, a gate insulating layer on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. - View Dependent Claims (17, 18, 19, 20)
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Specification