III-V FIELD EFFECT TRANSISTOR (FET) AND III-V SEMICONDUCTOR ON INSULATOR (IIIVOI) FET, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE

• US 20120248502A1
• Filed: 03/29/2011
• Published: 10/04/2012
• Est. Priority Date: 03/29/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Cheng-Wei, Han, Shu-Jen, Lee, Ko-Tao, Shiu, Kuen-Ting
• Granted Patent: US 8,828,824 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Abstract

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.

Claims

1. A method of forming Field Effect Transistors (FETs), said method comprising:

defining FET locations on a layered semiconductor wafer, one or more defined FETs having exposed channel ends;

converting portions of a buried layer beneath source/drain contact regions at said exposed channel ends to a dielectric material;

forming channel end caps on channel sidewalls at opposite said exposed channel ends; and

forming source/drain contacts to said end caps.

2. A method of forming FETs as in claim 1, wherein defining FET locations comprises forming a gate in each FET location.

3. A method of forming FETs as in claim 2, wherein defining FET locations further comprises forming dielectric sidewalls along each gate.

4. A method of forming FETs as in claim 1, wherein converting portions comprises:

etching a surface layer to a buried layer of said layered semiconductor wafer; and

sub-etching an upper portion of said buried layer.

5. A method of forming FETs as in claim 4, wherein converting portions further comprises converting exposed sub-etched surfaces to a dielectric material layer.

6. A method of forming FETs as in claim 4, wherein the surface layer is a Gallium Arsenide (GaAs) layer, the buried layer is Aluminum Arsenide (AlAs) layer and the dielectric material is Aluminum Oxide (AlO).

7. A method of forming FETs as in claim 6, wherein the AlAs is converted to AlO and the AlO layer is greater than half the thickness of at least one FET such that AlO is under the GaAs layer for the entire at least one FET, the at least one FET being a III-V semiconductor on insulator (IIIVOI) device.

8. A method of forming FETs as in claim 5, wherein forming said end caps further comprises filling said source/drain contact regions with semiconductor material to the upper surface of the one or more FET channels.

9. A method of forming FETs as in claim 8, wherein filling said source/drain contact regions comprises:

forming a metal layer on said layered semiconductor wafer;

opening said metal layer at the gate of each of one or more defined FETs to electrically separate said gate from said metal layer; and

forming a semiconductor material source/drain region on remaining portions of said metal layer, said semiconductor material filling said source/drain contact regions to the top surface of the respective FET channel.

10. A method of forming FETs as in claim 1, wherein said FETs are devices in an Integrated Circuit (IC) chip, said source/drain contacts form above, and do not penetrate to the bottom of, said dielectric material in said buried layer, and said method further comprises forming chip wiring connecting said FETs into chip circuits and connecting said chip circuits together.

11. A method of forming Integrated Circuit (IC) chips, said method comprising:

defining Field Effect Transistor (FET) gates on a layered III-V semiconductor wafer;

removing said III-V semiconductor surface layer to a buried layer at source/drain regions of one or more defined FETs;

sub-etching partially through said buried layer at said source/drain regions;

replacing exposed sub-etched surfaces of said buried layer to a dielectric material layer;

forming channel end caps on side walls of the etched said III-V semiconductor surface layer;

filling sub-etched areas with semiconductor material;

forming source/drain contacts to said source/drain regions, said source/drain contacts being formed above said dielectric material; and

forming chip wiring to FET gates and source/drain contacts connecting said FETs into chip circuits and connecting said chip circuits together.

12. A method of forming FETs as in claim 11, wherein defining FET gates comprises forming a gate in each FET location and forming dielectric sidewalls along each gate.

13. A method of forming FETs as in claim 12, wherein the surface layer is Gallium Arsenide (GaAs), the buried layer is Aluminum Arsenide (AlAs) and the converted dielectric material is Aluminum Oxide (AlO).

14. A method of forming FETs as in claim 13, wherein the AlO layer is greater than half the thickness of at least one FET such that AlO is under the GaAs surface layer for the entire at least one FET, said at least one FET being a III-V on insulator (IIIVOI) device.

15. A method of forming FETs as in claim 13, wherein filling said sub-etched areas comprises forming a GaAS layer in said source/drain regions filling said sub-etched areas to an upper surface of said GaAS surface layer.

16. A Field Effect Transistor (FET) comprising:

a FET pedestal on a layered wafer, said FET pedestal comprising;

a III-V semiconductor island,

a buried layer in said layered wafer, said FET pedestal extending upward from said buried layer and supporting said III-V semiconductor island, and

a gate on said III-V semiconductor island;

a dielectric material surface layer in said buried layer surface along pedestal sidewalls and in a horizontal surface in source/drain regions adjacent to said FET pedestal;

a dielectric sidewall on along each end of said gate;

a sidewall cap on opposite sidewalls of said III-V semiconductor island at opposite ends of said gate; and

contacts to said source/drain regions.

17. A FET as in claim 16, wherein the surface layer is Gallium Arsenide (GaAs), the buried layer is Aluminum Arsenide (AlAs) and the dielectric material surface layer is Aluminum Oxide (AlO).

18. A FET as in claim 17, wherein the AlO layer is thicker than half the thickness of the GaAs layer in at least one FET, such that said at least one FET is a III-V on insulator (IIIVOI) device.

19. A FET as in claim 17, further comprising a heavily doped semiconductor material filling source/drain regions to the upper surface of said surface layer, said heavily doped semiconductor material being source/drain doped to a concentration higher than sidewall caps.

20. A FET as in claim 19, further comprising a metal layer along said AlO layer, said heavily doped semiconductor material being on said metal layer and wherein said heavily doped semiconductor material is selected from Indium Arsenide (InAs) and InGaAs.

21. An Integrated Circuit (IC) chip comprising:

a semiconductor substrate;

a buried layer on said semiconductor substrate;

a III-V semiconductor surface layer on said buried layer;

a plurality of Field Effect Transistors (FETs) on said III-V semiconductor surface layer connected into a plurality of IC chip circuits, one or more of said FETs comprising;

a FET pedestal, each FET pedestal extending upward from said buried layer and supporting a III-V semiconductor island,

a gate on said III-V semiconductor island,

a dielectric sidewall on III-V semiconductor island along each end of said gate, and

a doped semiconductor cap on a sidewall of said at each end of said gate;

a dielectric material surface layer in the surface of said buried layer along pedestal sidewalls and in a buried layer horizontal surface in source/drain regions adjacent to said FET pedestal,

contacts to said source/drain regions; and

one or more wiring layers, at least one wiring layer connecting to FET source/drain contacts, wiring in said wiring layers further connecting said FETs into said plurality of IC chip circuits.

22. An IC as in claim 21, wherein said, wherein the III-V semiconductor is Gallium Arsenide (GaAs), the buried layer is an Aluminum Arsenide (AlAs) layer and the dielectric material is Aluminum Oxide (AlO).

23. A IC as in claim 22, wherein the AlO layer is thicker than half the thickness of the GaAs layer in at least one FET, such that said at least one FET is a III-V on insulator (IIIVOI) device.

24. An IC as in claim 22, wherein said heavily doped semiconductor material is selected from Indium Arsenide (InAs) and InGaAs, said heavily doped semiconductor material being source/drain doped to a concentration higher than sidewall caps and said one or more FET contacts to said source/drain regions terminate in or above said dielectric material.

25. An IC as in claim 22, further comprising a metal layer along said AlO layer.