SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER

• US 20120248511A1
• Filed: 04/01/2011
• Published: 10/04/2012
• Est. Priority Date: 04/01/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Guo, Ted Ming-Lang, Chien, Chin-Cheng, Chan, Shu-Yen, Chou, Ling-Chun, Chang, Tsung-Hung, Wu, Chun-Yuan
• Granted Patent: US 8,502,288 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Claims

1. A semiconductor structure comprising:

a substrate; and

a gate structure disposed on said substrate, said gate structure comprising;

a gate dielectric layer disposed on said substrate;

a gate material layer disposed on said gate dielectric layer; and

an outer spacer with a rectangular cross section, wherein the top surface of said outer spacer is lower than the top surface of said gate material layer;

a set of source and drain disposed in said substrate and adjacent to said outer spacer; and

an interlayer dielectric layer covering said substrate, said gate structure and said set of source and drain.

2. The semiconductor structure of claim 1, wherein the width of said outer spacer is larger than the height of said outer spacer.

3. The semiconductor structure of claim 1, wherein the top surface of said outer spacer is discontinuously lower than the top surface of said gate material layer.

4. The semiconductor structure of claim 1, further comprising:

a contact etching-stop layer disposed on said substrate and having a stress.

5. The semiconductor structure of claim 1, wherein said gate structure further comprises:

an inner spacer in direct contact with said gate dielectric layer and said gate material layer.

6. The semiconductor structure of claim 1, wherein said gate structure further comprises:

a middle spacer adjacent to said gate dielectric layer and said gate material layer and with an L cross section.

7. A method for lowering the height of a spacer, comprising:

providing a gate structure disposed on a substrate, said gate structure comprising;

a gate dielectric layer disposed on said substrate;

a gate material layer disposed on said gate dielectric layer; and

an outer spacer with a sail-like cross section and adjacent to said gate dielectric layer and said gate material layer; and

performing an oxidative slimming procedure to slim the height of said outer spacer without substantially slimming the width of said outer spacer to make said outer spacer have a rectangular cross section.

8. The method for lowering the height of a spacer of claim 7, wherein said oxidative slimming procedure involves at least one of a wet etching step and a dry etching step.

9. The method for lowering the height of a spacer of claim 7, wherein said oxidative slimming procedure involves at least one of a mixture of hydrogen peroxide and sulfuric acid, and an oxygen ashing step.

10. The method for lowering the height of a spacer of claim 7, wherein the slimed width of said outer spacer is one tenth less than the slimed height of said outer spacer.

11. The method for lowering the height of a spacer of claim 7, wherein the width of said rectangular cross section is larger than the height of said rectangular cross section.

12. The method for lowering the height of a spacer of claim 7, before said oxidative slimming procedure further comprising:

forming an inner spacer in direct contact with said gate material layer;

performing a lightly doping procedure to form a lightly doping region (LDD) in said substrate;

forming a middle spacer adjacent to said gate dielectric layer and said gate material layer and with an L cross section; and

performing a source/drain doping procedure to form a source/drain region in said substrate.

13. The method for lowering the height of a spacer of claim 7, after said oxidative slimming procedure further comprising:

forming a stress layer to cover said gate structure and said outer spacer;

constructing a stress in said substrate under said gate structure by means of said stress layer; and

removing said stress layer.

14. The method for lowering the height of a spacer of claim 13, further comprising:

forming a silicide on said substrate before removing said outer spacer with said rectangular cross section.

15. The method for lowering the height of a spacer of claim 7, before said oxidative slimming procedure further comprising:

forming a stress layer to cover said gate structure and said outer spacer;

constructing a stress in said substrate under said gate structure by means of said stress layer; and

removing said stress layer.

16. The method for lowering the height of a spacer of claim 7, after said oxidative slimming procedure further comprising:

forming a contact etch-stop layer to cover said gate structure;

forming an interlayer structure to cover said contact etch-stop layer; and

forming a contact plug to electrically connect said source/drain region under said interlayer structure.

17. The method for lowering the height of a spacer of claim 16, further comprising:

removing said outer spacer with said rectangular cross section before forming said contact etch-stop layer; and

forming a silicide on said substrate after a contact hole is formed for accommodating said contact plug.

18. The method for lowering the height of a spacer of claim 16, before forming said contact etch-stop layer further comprising:

forming a silicide on said substrate; and

removing said outer spacer with said rectangular cross section.

19. The method for lowering the height of a spacer of claim 7, wherein the top surface of said outer spacer is discontinuously lower than the top surface of said gate material layer.