METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY

• US 20120248529A1
• Filed: 04/01/2011
• Published: 10/04/2012
• Est. Priority Date: 04/01/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Jun, Tang, Sanh D., Wells, David H.
• Granted Patent: US 9,673,102 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

Claims

1. A method of forming a structure of a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, the method comprising:

forming the peripheral circuit transistor structures in the periphery region;

forming the plurality of array transistors in the array portion; and

forming a plurality of memory cells over respective array transistors,

wherein an upper surface of the periphery region and an upper surface of the array portion are nearly planar after formation of the peripheral circuit transistor structures and the plurality of memory cells.

2. The method of claim 1, wherein the upper surface of the periphery region and the upper surface of the array portion are within 500 Å

of average elevation after formation of the peripheral circuit transistor structures and the plurality of memory cells.

3. The method of claim 1, wherein the upper surface of the periphery region and the upper surface of the array portion are within 200 Å

of average elevation after formation of the peripheral circuit transistor structures and the plurality of memory cells

4. The method of claim 1, wherein the plurality of array transistors is formed after the peripheral circuit transistor structures is formed.

5. The method of claim 1, wherein the plurality of array transistors and the peripheral circuit transistor structures are formed concurrently.

6. The method of claim 1, wherein the array transistors are vertical transistors with self-aligned contacts.

7. The method of claim 1, wherein forming the peripheral circuit transistor structures comprises:

forming a pad oxide on a substrate;

forming a nitride on the pad oxide;

forming at least one first trench in the periphery region;

filling the at least one first trench with a dielectric material to form a shallow trench isolation region;

forming at least one transistor in the periphery region; and

removing the nitride.

8. The method of claim 1, wherein forming the plurality of array transistors comprises:

doping an upper surface of the substrate in the array portion;

forming an oxide over the array portion and the periphery region, wherein the oxide extends above an upper surface of the peripheral circuit transistor structures;

forming a plurality of second trenches in the array portion, the plurality of second trenches extending through the oxide to the doped upper surface of the substrate;

growing epitaxial silicon within the plurality of second trenches;

forming a resist material on the array portion, in a direction perpendicular to a direction of formation of the plurality of second trenches, and forming the resist material over the entire periphery region;

etching unmasked areas of the oxide and unmasked areas of the epitaxial silicon within the second trenches to form a plurality of third trenches, the plurality of third trenches extending through the oxide and epitaxial silicon to the doped upper surface of the substrate, resulting in a plurality of silicon pillars in the array portion;

removing the resist material;

forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the substrate; and

forming side gates on the gate oxide.

9. The method of claim 8, wherein the doped upper surface of the substrate has n-type doping.

10. The method of claim 8, wherein the oxide formed over the array portion and the periphery region is silicon dioxide.

11. The method of claim 8, wherein forming the side gates comprises:

depositing a gate material on sides of the gate oxide covered silicon pillars;

etching the gate material to be recessed below a top surface of the gate oxide covered silicon pillars, thereby forming strips of the gate material.

12. The method of claim 11, wherein the gate material is TiN.

13. The method of claim 11, wherein the gate material is deposited by ALD and the gate material is etched via a spacer etch process.

14. The method of claim 1, wherein forming the plurality of array transistors comprises:

doping an upper surface of the substrate in the array portion;

forming an oxide over the array portion and the periphery region, wherein the oxide layer extends above an upper surface of the peripheral circuit transistor structures;

forming a plurality of columns through the oxide to the doped upper surface of the substrate;

growing epitaxial silicon within the plurality of columns to form the plurality of silicon pillars;

etching the oxide to expose sides of the plurality of silicon pillars;

forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the substrate; and

forming all around gates on the silicon pillars.

15. The method of claim 14, wherein forming the all around gates comprises:

depositing a gate material on the gate oxide;

etching the gate material to be recessed below a top surface of the gate oxide, thereby forming the gate material surrounding each of the silicon pillars.

16. The method of claim 15, wherein the gate material is TiN.

17. The method of claim 1, wherein forming the plurality of memory cells comprises:

recessing an upper surface of the silicon pillars;

forming a plurality of silicide contacts by silicidation of the silicon pillars;

depositing a phase-change material over the silicide contacts.

18. The method of claim 16, wherein the phase-change material is GST.

19. The method of claim 1, wherein forming the plurality of memory cells comprises:

recessing an upper surface of the silicon pillars;

depositing metal in the recessed upper surface of the silicon pillars;

recessing an upper surface of the deposited metal; and

depositing a phase-change material over the metal contacts.

20. The method of claim 1, wherein forming the peripheral circuit transistor structures and forming the plurality of array transistors comprises:

forming a pad oxide on a silicon substrate;

forming a nitride on the pad oxide;

forming at least one first trench in the periphery region, for formation of shallow trench isolation regions, and a plurality of second trenches in the array portion;

doping the silicon substrate in the periphery region for transistor structure formation;

doping the silicon substrate in the array region;

depositing an oxide into the at least one first trench and the plurality of second trenches, and planarizing the oxide to a top surface of the nitride;

forming a resist material on the array portion, in a direction perpendicular to a direction of formation of the plurality of second trenches, and forming the resist material over the entire periphery region;

etching unmasked areas of the array portion to form a plurality of third trenches, the plurality of third trenches extending through the nitride, the pad oxide, the oxide in the first trench and the silicon substrate to the doped array portion of the silicon substrate, resulting in a plurality of silicon pillars in the array portion;

removing the resist material;

forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the substrate; and

forming gates on the silicon pillars;

removing the nitride and the pad oxide from the periphery region;

forming at least one transistor structure in the periphery region, wherein a top surface of the at least one transistor structure is planar with an upper surface of the nitride and the oxide in the array; and

removing the nitride and the pad oxide from the array portion, thereby forming a plurality of self-aligned contact areas in the array portion.

21. The method of claim 20, wherein forming the gates comprises:

depositing a gate material on sides of the gate oxide formed on the silicon pillars;

etching the gate material to be recessed below a top surface of the silicon pillars, thereby forming the gates.

22. The method of claim 20, wherein the gate material is TiN.

23. The method of claim 1, wherein forming the peripheral circuit transistor structures and forming the plurality of array transistors comprises:

forming shallow trench isolation regions in a substrate in the periphery region;

forming a gate oxide;

forming a gate stack over the gate oxide in the periphery region;

forming a nitride spacer on a side surface of the gate stack between the periphery region and the array portion;

doping an upper surface of the substrate in the array portion;

growing epitaxial silicon in the array portion, wherein the epitaxial silicon is grown to a level of an upper surface of the gate stack;

forming a nitride cap over the array portion and the periphery region;

forming at least one transistor structure in the periphery region;

patterning the epitaxial silicon in the array portion;

forming a gate oxide on exposed surfaces of the epitaxial silicon;

forming gates;

depositing an oxide to gap fill the array portion and planarizing the oxide to the nitride cap; and

forming a plurality of self-aligned contacts for the plurality of array transistors.

24. The method of claim 23, wherein forming the at least one transistor structure further results in formation of a dummy hedge between the periphery region and the array portion.

25. The method of claim 23, wherein forming the gate stack comprises:

forming a polysilicon;

forming a metal;

forming a nitride; and

etching the polysilicon, metal and nitride to remove the polysilicon, metal and nitride from above the array portion, stopping on the gate oxide.

26. The method of claim 23, wherein patterning the epitaxial silicon in the array portion comprises:

forming a first plurality of trenches through the nitride and the epitaxial silicon;

depositing an oxide material for gap filling the trenches and covering the peripheral circuit transistor structures;

forming a second plurality of trenches through the deposited oxide material, the nitride and the epitaxial silicon, the second plurality of trenches arranged perpendicularly to the first plurality of trenches; and

removing the oxide material from above the nitride.

27. The method of claim 26, further comprising removing the oxide material from between silicon pillars formed by forming the first and second pluralities of trenches.

28. The method of claim 26, wherein forming the gates comprises:

depositing a metal gate material in the second plurality of trenches; and

spacer etching the metal gate material to be recessed below a surface of the epitaxial silicon.

29. The method of claim 26, wherein forming the gates comprises:

depositing a metal gate material in spaces between the silicon pillars; and

spacer etching the metal gate material to be recessed below a surface of the silicon pillars.

30. The method of claim 23, wherein forming the plurality of self-aligned contacts comprises:

forming an oxide cap over the peripheral circuit transistor structures;

removing the nitride cap from above the silicon pillars; and

doping an upper surface of the silicon pillars.

31. A memory device structure comprising:

peripheral circuit transistor structures formed above the substrate in a periphery region;

a plurality of array transistors formed above the substrate in an array region; and

a plurality of memory cells formed over respective array transistors,

wherein an upper surface of the periphery region comprising the peripheral circuit transistor structures and an upper surface of the array region comprising the plurality of array transistors and memory cells are nearly planar.

32. The memory device structure of claim 31, wherein the peripheral circuit transistor structures comprises at least one transistor structure.

33. The memory device structure of claim 31, wherein the array transistors are vertical transistors with self-aligned contacts.

34. The memory device structure of claim 32, wherein an upper surface of the at least one transistor structure is nearly planar with the upper surface of the periphery region.

35. The memory device structure of claim 32, wherein an upper surface of the at least one transistor structure is below the upper surface of the periphery region.

36. The memory device structure of claim 31, wherein each of the plurality of array transistors comprises a silicon pillar and a gate.

37. The memory device structure of claim 36, wherein a plurality of silicon pillars share a common gate.

38. The intermediate memory device structure of claim 36, wherein the silicon pillar for each of the plurality of array transistors has a corresponding gate that completely surrounds the silicon pillar.