INTERPOSER HAVING AN INDUCTOR

• US 20120248569A1
• Filed: 03/29/2011
• Published: 10/04/2012
• Est. Priority Date: 03/29/2011
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Jenkins, Michael O., Karp, James, Kireev, Vassili, Wu, Ephrem C.
• Granted Patent: US 8,823,133 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.

Claims

1. A multichip module, comprising:

a semiconductor die;

an interposer having conductive layers, dielectric layers, and a substrate;

a plurality of internal interconnect structures that couple the semiconductor die to the interposer;

a plurality of external interconnect structures that are for coupling the interposer to an external device;

a first inductor that comprises at least a portion of one or more of the conductive layers of the interposer;

a first end of the first inductor coupled to an internal interconnect structure of the plurality of internal interconnect structures; and

a second end of the first inductor coupled to an external interconnect structure of the plurality of external interconnect structures.

2. The multichip module according to claim 1, further comprising:

a second inductor coupled in series with the first inductor;

wherein the first inductor and the second inductor are positioned with respect to one another for inductive coupling during operation of the multichip module.

3. The multichip module according to claim 2, wherein an electrostatic discharge circuit is coupled at a node interconnecting the first inductor and the second inductor in the series.

4. The multichip module according to claim 3, wherein the interposer includes the electrostatic discharge circuit.

5. The multichip module according to claim 3, wherein the semiconductor die includes the electrostatic discharge circuit.

6. The multichip module according to claim 2, wherein the interposer includes both the first inductor and the second inductor.

7. The multichip module according to claim 2, wherein:

the interposer includes the first inductor; and

the semiconductor die includes the second inductor.

8. The multichip module according to claim 7, wherein:

the first inductor and the second inductor are part of a T-coil network; and

the T-coil network includes a capacitor coupled in parallel with the series formed by the first inductor and the second inductor.

9. The multichip module according to claim 8, wherein:

the capacitor has a first plate and a second plate;

the semiconductor die includes the first plate;

the interposer includes the second plate; and

the first plate and the second plate are positioned with respect to one another for capacitive coupling during operation of the multichip module.

10. The multichip module according to claim 9, wherein:

a bottom surface of the first plate is substantially coplanar with a top surface of the second plate;

the bottom surface is an external surface of the semiconductor die;

the top surface is an external surface of the interposer;

a gap is defined as between the bottom surface and the top surface; and

the gap is an air gap provided at least in part by the internal interconnect structures offsetting the semiconductor die from the interposer.

11. The multichip module according to claim 10, wherein:

the semiconductor die includes an electrostatic discharge circuit; and

the electrostatic discharge circuit is coupled at a node interconnecting the first inductor and the second inductor in the series.

12. The multichip module according to claim 11, further comprising:

a driver circuit of the semiconductor die connected to the node;

the driver circuit selected from a group consisting of an input driver, an output driver, and an input/output driver;

a termination circuit of the semiconductor die connected to a first end of the second inductor;

the first plate connected to the first end of the second inductor; and

a second end of the second inductor connected to the node.

13. The multichip module according to claim 2, wherein:

the second inductor is coupled to a driver circuit of the semiconductor die; and

the driver circuit is selected from a group consisting of an input driver, an output driver, and an input/output driver.

14. The multichip module according to claim 2, wherein:

the first inductor is coupled to a driver circuit of the semiconductor die; and

the driver circuit is selected from a group consisting of an input driver, an output driver, and an input/output driver.

15. A multichip module, comprising:

an interposer having a first inductor and a first plate of a capacitor;

a semiconductor die having a second inductor and a second plate of the capacitor; and

the interposer and the semiconductor die interconnected to one another for coupling the first inductor and the second inductor in series;

wherein the interposer and the semiconductor die are positioned relative to one another for inductive coupling between the first inductor and the second inductor and for capacitive coupling between the first plate and the second plate during operation of the T-coil network.

16. The multichip module according to claim 15, wherein:

a surface of each of the first plate and the second plate define an air gap between them associated with an offset between the semiconductor die and the interposer; and

the first plate, the second plate, and the air gap provide a capacitor coupled in parallel with the series formed by the first inductor and the second inductor.

17. The multichip module according to claim 16, wherein:

the semiconductor die includes an electrostatic discharge circuit; and

the electrostatic discharge circuit is coupled to a node located between the first inductor and the second inductor.

18. A transceiver, comprising:

a T-coil network;

wherein the T-coil network includes;

a first inductor and a second inductor coupled in series;

a capacitor coupled in parallel with the series formed by the first inductor and the second inductor;

an interposer that includes the first inductor;

a semiconductor die that includes the second inductor; and

the interposer and the semiconductor die interconnected to one another;

wherein the first inductor and the second inductor are positioned relative to one another for inductive coupling during operation of the transceiver.

19. The transceiver according to claim 18, wherein

the interposer has a first plate of the capacitor;

the semiconductor die has a second plate of the capacitor; and

the interposer and the semiconductor die are interconnected such that the first plate and the second plate are separated from one another and are capacitively coupled to one another during operation.

20. The transceiver according to claim 19, wherein a node located between the first inductor and the second inductor is connected to a gate of a driver transistor of the transceiver.