SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20120248610A1
• Filed: 03/20/2012
• Published: 10/04/2012
• Est. Priority Date: 03/31/2011
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KIKUSHIMA, Fumie
• Application Number:
  US13/424,802
• Publication Number:
  US 20120248610A1
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

According to one embodiment, a semiconductor memory device comprises: a semiconductor substrate; a first contact plug and a second contact plug on the semiconductor substrate; a first bit line being in contact with the first contact plug; and a second bit line on the second contact plug, wherein the first contact plug is in contact with a top surface of the first bit line and is electrically insulated from the second bit line, and a bottom surface of the second bit line is higher in height than the top surface of the first bit line.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate;

a first contact plug and a second contact plug provided on the semiconductor substrate; and

a first bit line being in contact with the first contact plug, and a second bit line provided on the second contact plug,

wherein the first contact plug is in contact with a top surface of the first bit line and is electrically insulated from the second bit line, and

a bottom surface of the second bit line is higher in height than the top surface of the first bit line.

2. The semiconductor memory device according to claim 1, wherein the first contact plug is further in contact with a side surface of the first bit line.

3. The semiconductor memory device according to claim 1, wherein the first bit line is shifted in a second direction in a region where the first bit line and the first contact plug intersect each other.

4. The semiconductor memory device according to claim 3, wherein the first bit line is shifted in the second direction by a distance substantially equal to half a diameter of a top surface of the first contact plug.

5. The semiconductor memory device according to claim 1, wherein

a plurality of the first contact plugs and a plurality of the second contact plugs are each arranged at periodic intervals in the second direction, and

the first contact plugs and the second contact plugs are arranged in a staggered pattern.

6. The semiconductor memory device according to claim 1, wherein

a diameter of a bottom surface of the first contact plug is substantially equal to that of a bottom surface of the second contact plug, and

a diameter of a top surface of the second contact plug is substantially half a diameter of a top surface of the first contact plug.

7. The semiconductor memory device according to claim 1, wherein a cross-sectional shape of the first bit line is substantially rectangular.

8. The semiconductor memory device according to claim 1, wherein a height of the first contact plug is substantially equal to that of the second contact plug.

9. The semiconductor memory device according to claim 1, wherein each of the first bit line and the second bit line is formed of a wiring layer and a barrier metal film covering the wiring layer.

10. The semiconductor memory device according to claim 1, wherein each of the first contact plug and the second contact plug is a tungsten film.

11. The semiconductor memory device according to claim 9, wherein the wiring layer is a Cu layer.

12. A method of fabricating a semiconductor memory device, comprising:

forming a first insulating film on a semiconductor substrate;

forming a second insulating film on the first insulating film;

processing the second insulating film to form a first wiring trench;

forming a first bit line in the first wiring trench;

forming a third insulating film on the second insulating film and the first bit line;

processing the third insulating film, the second insulating film, and the first insulating film to form a first contact hole and a second contact hole and also to expose a top surface of the first bit line through the first contact hole;

burying a first contact plug into the first contact hole, and a second contact plug into the second contact hole;

forming a fourth insulating film on the third insulating film, the first contact plug, and the second contact plug;

processing the fourth insulating film to form a second wiring trench on the second contact plug; and

forming a second bit line in the second wiring trench.

13. The method of fabricating a semiconductor memory device according to claim 12, wherein a side surface of the first bit line is also exposed in the forming of the first contact hole.

14. The method of fabricating a semiconductor memory device according to claim 12, wherein

a plurality of the first contact holes and a plurality of the second contact holes are each formed at periodic intervals in a second direction, and

the first contact plugs and the second contact plugs are formed in a staggered pattern.

15. The method of fabricating a semiconductor memory device according to claim 12, wherein in the forming of the first contact hole, the top surface of the first bit line is exposed by an area substantially equal to one half of a top surface of the first contact plug that is defined by a diameter thereof.

16. The method of fabricating a semiconductor memory device according to claim 12, wherein a height of the first contact hole is substantially equal to that of the second contact hole.

17. The method of fabricating a semiconductor memory device according to claim 12, wherein

the second insulating film is a stacked film in which a first stopper film and an interlayer insulating film are stacked in this order,

the first stopper film has an etch selectivity to the first insulating film,

the third insulating film is a second stopper film, and

the second stopper film has an etch selectivity to the interlayer insulating film.