METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

• US 20120248622A1
• Filed: 03/31/2011
• Published: 10/04/2012
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Inventors: Sadaka, Mariam
• Granted Patent: US 8,338,294 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80097 Heating
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/15 : Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are formed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate, the substrate comprising a layer of semiconductor material on a layer of electrically insulating material;

forming a first metallization layer comprising a plurality of electrically conductive features on the substrate over a first side of the layer of semiconductor material opposite the layer of electrically insulating material;

forming a plurality of through wafer interconnects at least partially through the substrate, and forming at least one through wafer interconnect of the plurality of through wafer interconnects to extend through each of the metallization layer and the layer of semiconductor material;

forming a second metallization layer comprising a plurality of electrically conductive features over a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material; and

providing an electrical pathway extending continuously through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material.

2. The method of claim 1, wherein providing the substrate comprises selecting the substrate to comprise a semiconductor-on-insulator (SeOI) substrate.

3. The method of claim 2, wherein selecting the substrate to comprise a semiconductor-on-insulator (SeOI) substrate comprises selecting the substrate to comprise a silicon-on-insulator (SOI) substrate.

4. The method of claim 2, wherein the layer of semiconductor material has an average total thickness of about one micron or less, and wherein the layer of electrically insulating material comprises a layer of oxide material having an average total thickness of about one 300 nm or less.

5. The method of claim 1, wherein forming the at least one through wafer interconnect of the plurality of through wafer interconnects to extend through each of the metallization layer and the layer of semiconductor material further comprises forming the at least one through wafer interconnect of the plurality of through wafer interconnects to extend through the layer of electrically insulating material.

6. The method of claim 1, further comprising bonding at least one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate over the first side of the layer of semiconductor material.

7. The method of claim 6, wherein bonding at least one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate over the first side of the layer of semiconductor material comprises directly bonding the at least one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate in a metal-to-metal direct bonding process at a temperature or temperatures below about 400°

C.

8. The method of claim 1, further comprising forming at least one of the first processed semiconductor structure and the second processed semiconductor structure in situ on the substrate over the first side of the layer of semiconductor material.

9. The method of claim 1, wherein providing an electrical pathway further comprises configuring the electrical pathway to extend through at least one conductive feature of the first metallization layers, through the at least one through wafer interconnect of the plurality of through wafer interconnects extending through each of the metallization layer and the layer of semiconductor material, through at least one conductive feature of the second metallization layer, and through at least another through wafer interconnect of the plurality of through wafer interconnects.

10. The method of claim 1, further comprising structurally and electrically connecting at least one conductive feature of the second metallization layer to a conductive feature of another substrate.

11. The method of claim 1, further comprising individually selecting each of the first processed semiconductor structure and the second processed semiconductor structure from the group consisting of an electronic signal processor device, an electronic memory device, an electromagnetic radiation emitter device, and an electromagnetic radiation receiver device.

12. The method of claim 11, further comprising:

selecting the first processed semiconductor structure to comprise an electronic signal processor device; and

selecting the second processed semiconductor structure to comprise at least one of an electronic memory device, a light-emitting diode, a laser-emitting diode, and a solar cell.

13. A semiconductor structure, comprising:

a substrate comprising a layer of semiconductor material;

a first metallization layer on the substrate over a first side of the layer of semiconductor material;

a second metallization layer on the substrate over a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material;

a plurality of through wafer interconnects extending at least partially through each of the first metallization layer and the layer of semiconductor material of the substrate;

a first processed semiconductor structure carried by the substrate over the first side of the layer of semiconductor material; and

a second processed semiconductor structure carried by the substrate over the first side of the layer of semiconductor material;

wherein an electrical pathway extends from the first processed semiconductor structure, through a conductive feature of the first metallization layer, through a first through wafer interconnect of the plurality of through wafer interconnects, through a conductive feature of the second metallization layer, and through a second through wafer interconnect of the plurality of through wafer interconnects to the second processed semiconductor structure.

14. The semiconductor structure of claim 13, wherein the substrate comprises a semiconductor-on-insulator (SeOI) substrate.

15. The semiconductor structure of claim 14, wherein the semiconductor-on-insulator (SeOI) substrate comprises a silicon-on-insulator (SOI) substrate.

16. The semiconductor structure of claim 14, wherein the layer of semiconductor material has an average total thickness of about one micron or less.

17. The semiconductor structure of claim 14, wherein at least one through wafer interconnect of the plurality of through wafer interconnects extends at least partially through a layer of electrically insulating material of the SeOI substrate.

18. The semiconductor structure of claim 13, wherein at least one of the first processed semiconductor structure and the second processed semiconductor structure is bonded to the substrate over the first side of the layer of semiconductor material.

19. The semiconductor structure of claim 18, wherein a metal feature of the at least one of the first processed semiconductor structure and the second processed semiconductor structure is directly bonded to at least one through wafer interconnect of the plurality of through wafer interconnects.

20. The semiconductor structure of claim 13, wherein the electrical pathway extends continuously between the first processed semiconductor structure and the second processed semiconductor structure through the substrate, the first metallization layer, and the second metallization layer.

21. The semiconductor structure of claim 13, wherein at least one conductive feature of the second metallization layer is electrically coupled to a conductive feature of another substrate.

22. The semiconductor structure of claim 13, wherein each of the first processed semiconductor structure and the second processed semiconductor structure comprises one of an electronic signal processor device, an electronic memory device, an electromagnetic radiation emitter device, and an electromagnetic radiation receiver device.

23. The semiconductor structure of claim 22, wherein:

the first processed semiconductor structure comprises an electronic signal processor device; and

the second processed semiconductor structure comprises at least one of an electronic memory device, a light-emitting diode, a laser-emitting diode, and a solar cell.