INDUCED THERMAL GRADIENTS

• US 20120249219A1
• Filed: 12/23/2011
• Published: 10/04/2012
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shoemaker, Kenneth D.
• Granted Patent: US 9,658,678 B2
• Time in Patent Office: Days
• US Class Current: 327/512
• CPC Class Codes: G01K 3/08 giving differences of values using thermoelectric elements G01K7/02; giving differentiated values
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

Claims

1. An apparatus comprising:

a second die having a first thermal sensor and a second thermal sensor;

a first die having a third thermal sensor, the second die in close physical proximity with the first die;

control logic coupled with the first thermal sensor and the second thermal sensor, the control logic to determine a temperature difference between the first thermal sensor and the second thermal sensor;

management logic coupled with the control logic and the thermal sensor on the first die, the management logic to receive the temperature difference and a temperature measurement from the thermal sensor on the first die, to determine a location for the third thermal sensor, and to manage operational characteristics of the first die based on the temperature difference communicated from the second die and the temperature measurement from the thermal sensor on the first die.

2. The apparatus of claim 1 wherein the control logic further comprises a register to store one or more bits to indicate the location of the third thermal sensor.

3. The apparatus of claim 1 wherein the management logic further comprises a register to store one or more bits to indicate the location of the third thermal sensor.

4. The apparatus of claim 1 wherein the first die comprises a dynamic random access memory (DRAM) array.

5. The apparatus of claim 4 wherein the management logic modifies refresh rates of the DRAM array based on the temperature gradient on the second die and the temperature measurement from the thermal sensor on the first die.

6. The apparatus of claim 4 wherein the second die comprises a processor core.

7. The apparatus of claim 4 wherein the second die comprises a system on a chip (SoC).

8. A system comprising:

wireless transceiver circuitry coupled with an antenna;

a second die having a first thermal sensor and a second thermal sensor;

a first die having a third thermal sensor, the second die in close physical proximity with the first die;

control logic coupled with the first thermal sensor and the second thermal sensor, the control logic to determine a temperature difference between the first thermal sensor and the second thermal sensor;

management logic coupled with the control logic and the thermal sensor on the first die, the management logic to receive the temperature difference and a temperature measurement from the thermal sensor on the first die, to determine a location for the third thermal sensor, and to manage operational characteristics of the first die based on the temperature difference communicated from the second die and the temperature measurement from the thermal sensor on the first die.

9. The system of claim 8 further comprising a touch screen interface coupled with the first die.

10. The system of claim 8 wherein the control logic further comprises a register to store one or more bits to indicate the location of the third thermal sensor.

11. The system of claim 8 wherein the management logic further comprises a register to store one or more bits to indicate the location of the third thermal sensor.

12. The system of claim 8 wherein the first die comprises a dynamic random access memory (DRAM) array.

13. The system of claim 12 wherein the management logic modifies refresh rates of the DRAM array based on the temperature difference and the temperature measurement from the thermal sensor on the first die.

14. The system of claim 12 wherein the second die comprises a processor core.

15. The system of claim 12 wherein the second die comprises a system on a chip (SoC).

16. A method comprising:

determining a temperature difference between a first thermal sensor and a second thermal sensor on a first die;

determining a location for a thermal sensor on a second die;

transmitting the temperature difference from the first die to a circuit on the second die;

determining a temperature from the thermal sensor on the second die;

utilizing the temperature difference, the location of the thermal sensor on the second die, and the temperature from the thermal sensor on the second die to modify operational characteristics of one or more circuits on the second die.

17. The method of claim 16 wherein the second die comprises a dynamic random access memory (DRAM) array.

18. The method of claim 17 wherein the circuit modifies refresh rates of the DRAM array based on the temperature measurement from the thermal sensor on the second die.

19. The method of claim 17 wherein the first die comprises a processor core.

20. The method of claim 17 wherein the first die comprises a system on a chip (SoC).

21. A semiconductor device comprising:

a memory die having a dynamic random access memory (DRAM) array, a mode register including a storage location for a thermal offset bit, and a memory thermal sensor electrically coupled to the DRAM array;

a controller die thermally coupled with the memory die, the controller die including at least one thermal sensor to detect a thermal offset and circuitry to provide the thermal offset bit to the storage location for the thermal offset bit of the mode register on the memory die responsive to detecting a change in the thermal offset;

a temperature compensated self-refresh (TCSR) circuit located on the memory die, the TCSR circuit operable to modify a self-refresh rate of the memory array responsive, at least in part, to the thermal offset bit.

22. The semiconductor device of claim 21 wherein the controller die includes an application processor.

23. The semiconductor device of claim 23 further comprising a touch screen coupled with the controller die.