VARIABLE MEMORY REFRESH DEVICES AND METHODS

• US 20120250388A1
• Filed: 06/11/2012
• Published: 10/04/2012
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Joe M. Jeddeloh
• Original Assignee: Joe M. Jeddeloh
• Inventors: Jeddeloh, Joe M.
• Granted Patent: US 8,797,818 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate.

Claims

1. A memory device, comprising:

a number of memory cells within a stacked memory array;

a logic die to manage refresh rates in the stacked memory array; and

a tracker to track a power down state for different portions, wherein the tracked power down states are used to refresh different portions within the stacked memory array at different refresh rates.

2. The memory device of claim 1, wherein the tracker further tracks an error rate in the different portions.

3. The memory device of claim 2, wherein the tracker further includes logic to utilize a redundant memory region if an error rate in one or more different portions falls below a selected error rate.

4. The memory device of claim 1, wherein the tracker further includes interconnect repair logic to re-route memory operations around defective through wafer interconnects.

5. The memory device of claim 1, wherein the logic die is attached to the stack of memory dies.

6. A memory device, comprising:

a number of memory cells within a stacked memory array;

a logic die to manage refresh rates in the stacked memory array; and

an error tracker to track an error rate for different portions, wherein the tracked error rate is used to refresh different portions within the stacked memory array at different refresh rates.

7. The memory device of claim 6, wherein the refresh rate of the respective one of the portions is also adjusted using another characteristic of the memory device.

8. The memory device of claim 7, wherein the other characteristic includes a sensed temperature of the respective one of the portions.

9. The memory device of claim 7, wherein the other characteristic includes a power down state for the different portions.

10. A memory device, comprising:

a stack of memory dies;

a logic die to manage refresh rates in the stack of memory dies; and

a memory map to refresh different portions within the stack of memory dies at different refresh rates.

11. The memory device of claim 10, wherein the different refresh rates are set at manufacture of the memory device.

12. The memory device of claim 10, wherein the different refresh rates are set at power up of the memory device.

13. The memory device of claim 10, wherein the different refresh rates are based on error rate.

14. The memory device of claim 10, wherein the logic die is attached to the stack of memory dies.

15. The memory device of claim 10, wherein the memory map is configured such that a first die in the stack of memory dies can be refreshed at a different rate from a second die in the stack of memory dies.

16. The memory device of claim 10, wherein the memory map is configured such that a first vault in the stack of memory dies can be refreshed at a different rate from a second vault in the stack of memory dies.

17. The memory device of claim 10, wherein the memory map is configured such that a first tile in the stack of memory dies can be refreshed at a different rate from a second tile in the stack of memory dies.