SEMICONDUCTOR MEMORY APPARATUS

• US 20120250402A1
• Filed: 12/30/2011
• Published: 10/04/2012
• Est. Priority Date: 03/30/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: SONG, Taek Sang, KWON, Dae Han
• Granted Patent: US 8,804,412 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Claims

1. A semiconductor memory apparatus comprising:

a resistive memory cell;

a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and

a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

2. The semiconductor memory apparatus according to claim 1, wherein the first and second resistors are designed in such a manner as to have the same characteristic by modeling a resistor included in the resistive memory cell.

3. The semiconductor memory apparatus according to claim 2, wherein the resistor included in the resistive memory cell has the first or second resistance value depending on a data value stored therein.

4. The semiconductor memory apparatus according to claim 3, wherein the resistor is formed of phase change material.

5. The semiconductor memory apparatus according to claim 1, wherein the reference voltage has a level in accordance with an intermediate value between the first resistance value and the second resistance value, and the sensing current.

6. The semiconductor memory apparatus according to claim 1, wherein the first and second resistors have the same resistance change amount as a resistor included in the resistive memory cell, according to a PVT (Process Voltage Temperature) variation.

7. The semiconductor memory apparatus according to claim 1, wherein the data sensing unit comprises:

is a first sensing current supply unit configured to supply a first sensing current to the resistive memory cell; and

a comparison unit configured to compare the reference voltage with the output voltage formed by the first sensing current supplied to the resistive memory cell, and decide the value of the output data according to the comparison result.

8. The semiconductor memory apparatus according to claim 7, further comprising a first data transmission unit inserted between the first sensing current supply unit and the resistive memory cell and configured to control an amount of current for the resistive memory cell according to a voltage level of a selection signal.

9. The semiconductor memory apparatus according to claim 7, wherein the reference voltage generation unit comprises:

the dummy memory cell comprising the first and second resistors coupled in parallel; and

a second sensing current supply unit configured to supply a second sensing current having the same magnitude as the first sensing current, to the dummy memory cell.

10. The semiconductor memory apparatus according to claim 9, further comprising a second data transmission unit inserted between the second sensing current supply unit and the dummy memory cell and configured to control an amount of current for the dummy memory cell according to the voltage level of a selection signal.

11. A semiconductor memory apparatus comprising:

a resistive memory cell;

a first data transmission unit configured to control an amount of current for the resistive memory cell according to a voltage level of a selection signal;

a data sensing unit configured to sense a first output voltage formed by a sensing current supplied to the resistive memory cell through the first data transmission unit, based on a reference voltage, and output data having a value corresponding to the sensing result;

a dummy memory cell comprising first and second resistors coupled in parallel to each other and having first and second resistance values, respectively; and

a second data transmission unit configured to control an amount of current for the dummy memory cell according to the voltage level of the selection signal and output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage,

wherein the reference voltage has a level in accordance with an intermediate value between the first resistance value and the second resistance value, and the sensing current.

12. The semiconductor memory apparatus according to claim 11, wherein the first and second resistors are designed in such a manner as to have the same characteristic by modeling a resistor included in the resistive memory cell.

13. The semiconductor memory apparatus according to claim 11, wherein a resistor included in the resistive memory cell has the first or second resistance value according to a data value stored therein.

14. The semiconductor memory apparatus according to claim 13, wherein the resistor is formed of a phase change material.

15. The semiconductor memory apparatus according to claim 11, wherein the first and second resistors are configured to have the same resistance change amount as a resistor included in the resistive memory cell, according to a PVT variation.

16. A semiconductor memory apparatus comprising:

a resistive memory cell having a first or second resistance value according to a data value stored therein;

a dummy memory cell comprising first and second resistor pairs coupled in parallel to each other and having resistance value of summation of the first resistance value and the second resistance value respectively; and

is a data sensing unit configured to sense an output voltage formed by a sensing current supplied to the resistive memory cell, based on a reference voltage formed by the sensing current supplied to the dummy memory cell, and decide a value of output data according to the sensing result,

wherein the reference voltage has a level in accordance with an intermediate value between the first resistance value and the second resistance value, and the sensing current.

17. The semiconductor memory apparatus according to claim 16, wherein the first resistor pair includes first and second resistors,

wherein the first and second resistors are designed in such a manner as to have the same characteristic by modeling a resistor included in the resistive memory cell.

18. The semiconductor memory apparatus according to claim 17, wherein a resistor included in the resistive memory cell is formed of a phase change material.

19. The semiconductor memory apparatus according to claim 17, wherein the first and second resistors are configured to have the same resistance change amount as a resistor included in the resistive memory cell, according to a PVT variation.