NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20120250420A1
• Filed: 12/19/2011
• Published: 10/04/2012
• Est. Priority Date: 04/01/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIRAKAWA, Masanobu, Sukegawa, Hiroshi
• Granted Patent: US 8,649,224 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

A control circuit performs a read operation of reading data held in a memory-cell by supplying a selected word-line with a read voltage that is a voltage between the lower limit and the upper limit of a plurality of threshold-voltage distributions provided to the memory-cell. The control circuit also performs a verify operation of determining whether a write operation is completed by supplying a selected word-line with a verify voltage higher than the read voltage to read the memory cell. The control circuit then performs a data variation determination operation of determining whether the memory-cells connected to a selected word-line each have a threshold voltage equal to or less than a certain value to determine, from among the plurality of memory cells connected to the selected word-line, whether the number of memory cells where data variation has occurred is not less than a certain number.

Claims

1. A non-volatile semiconductor memory device comprising;

a semiconductor substrate;

a memory string stacked above the semiconductor substrate and comprising a plurality of memory cells connected in series;

a drain-side select transistor connected to a first end of the memory string;

a source-side select transistor connected to a second end of the memory string;

a plurality of word lines connected to the memory cell;

a plurality of bit lines connected to the drain-side select transistor;

a source line connected to the source-side select transistor; and

a control circuit configured to control a voltage supplied to the drain-side select transistor, the source-side select transistor, the word lines, and the bit lines,

the control circuit being capable of performing a data variation determination operation of determining whether a plurality of memory cells connected to a selected word line each have a threshold voltage equal to or less than a certain value, and whether the number of memory cells where data variation has occurred is not less than a certain number.

2. The non-volatile semiconductor memory device according to claim 1, wherein

the data variation determination operation determines whether data variation has occurred by supplying a first voltage lower than a read voltage and a second voltage higher than the first voltage to a selected word line to read the memory cell.

3. The non-volatile semiconductor memory device according to claim 2, wherein

the second voltage is a voltage substantially equal to a read voltage.

4. The non-volatile semiconductor memory device according to claim 2, wherein

the control circuit is configured to determine that data variation has occurred in a memory cell that turned off when the first voltage is applied thereto and turned on when the second voltage is applied thereto.

5. The non-volatile semiconductor memory device according to claim 4, wherein

the second voltage is a voltage substantially equal to a read voltage.

6. The non-volatile semiconductor memory device according to claim 4, further comprising:

a first latch circuit configured to hold first data read by supplying the first voltage to the word line;

a second latch circuit configured to hold second data read by supplying the second voltage to the word line;

an arithmetic circuit supplying an arithmetic operation to data including the first data and the second data; and

a third latch circuit configured to hold third data related to the arithmetic result of the arithmetic circuit.

7. The non-volatile semiconductor memory device according to claim 1, wherein

if the data variation determination operation determines that the memory cells along a selected word line have a certain number of data variations or more, the control circuit is adapted to be able to perform an additional write operation by using a first command in order to return the threshold voltage distributions of the memory cells along the selected word line to a normal state.

8. The non-volatile semiconductor memory device according to claim 7, wherein

the control circuit is adapted to be able to perform, before performing the additional write operation, an additional write necessity determination operation identifying a memory cell for which the additional write operation is necessary.

9. The non-volatile semiconductor memory device according to claim 8, wherein

the data variation determination operation determines whether variation occurs in the upper limit or lower limit of the threshold voltage distributions by supplying a first voltage lower than a read voltage and a second voltage higher than the first voltage to a selected word line to read the memory cell, and

the additional write necessity determination operation determines the necessity of the additional write operation by supplying the first voltage and a third voltage higher than the second voltage to a selected word line to read the memory cell.

10. The non-volatile semiconductor memory device according to claim 9, wherein

the third voltage is the substantially same voltage as a verify voltage to determine the completion of the write operation to the memory cell.

11. The non-volatile semiconductor memory device according to claim 1, wherein

the data variation determination operation is first performed to, among the memory cells included in the memory string, a first memory cell in the bottom layer.

12. The non-volatile semiconductor memory device according to claim 11, wherein

if the data variation determination operation determines that the memory cells along a selected word line have a certain number of data variations or more, the control circuit is adapted to be able to perform an additional write operation by using a first command in order to return the threshold voltage distributions of the memory cells along the selected word line to a normal state, and

the control circuit ends, if the number of first memory cells in which data variation is determined to occur is less than a certain value, the data variation determination operation and the additional write operation.

13. The non-volatile semiconductor memory device according to claim 1, wherein

the data variation determination operation is performed only to the memory cell having a first threshold voltage distribution that is the maximum threshold voltage distribution among a plurality of threshold voltage distributions.

14. The non-volatile semiconductor memory device according to claim 1, wherein

the data variation determination operation is first performed to, among the memory cells included in the memory string, a third memory cell between a first memory cell in the bottom layer and a second memory cell in the top layer.

15. The non-volatile semiconductor memory device according to claim 1, wherein

the control circuit is adapted to supply, in the data variation determination operation, various levels of first voltages and various levels of second voltages to the word line in ascending order of voltage level.

16. The non-volatile semiconductor memory device according to claim 1, wherein

the control circuit starts the data variation determination operation from the memory cell formed at a lower part of the columnar semiconductor layer, and performs the data variation determination operation to the memory cells formed at an upper part of the columnar semiconductor layer in sequence.

17. The non-volatile semiconductor memory device according to claim 1, wherein

the control circuit is adapted to perform the data variation determination operation to a first word line connected to a first memory cell formed at a first position of the columnar semiconductor layer, and when it is determined, as a result of the data variation determination operation to the first word line, that a predetermined number of data variations or more has occurred in the memory cells, to perform a block copy operation of copying data stored in the memory block including the relevant first word line to a different memory block.

18. A method of controlling a non-volatile semiconductor memory device,

the non-volatile semiconductor memory device comprising a semiconductor substrate, a memory string extending in the vertical direction with respect to the semiconductor substrate and comprising a plurality of memory cells connected in series, a drain-side select transistor connected to a first end of the memory string, a source-side select transistor connected to a second end of the memory string, a plurality of word lines connected to the memory cell, a plurality of bit lines connected to the drain-side select transistor, and a source line connected to the source-side select transistor,

the method comprising:

executing a data variation determination operation of determining whether variation has occurred in the upper limit or lower limit of a plurality of threshold voltage distributions in each of the memory cells by supplying a first voltage lower than a read voltage and a second voltage higher than the first voltage to a selected word line to read the memory cell; and

executing, when the data variation determination operation determines that the memory cells along the selected word line have a certain number of data variations or more, an additional write operation of writing to return the threshold voltage distributions of the memory cells along the selected word line to a normal state.

19. The control method according to claim 18, wherein

the data variation determination operation determines that data variation has occurred in a memory cell that becomes non-conductive when the first voltage is applied thereto and becomes conductive when the second voltage is applied thereto.

20. The control method according to claim 18, wherein

before performing the additional write operation, an additional write necessity determination operation identifying a memory cell for which the additional write operation is necessary is performed.