SYSTEM ARCHITECTURE BASED ON FLASH MEMORY

• US 20120254501A1
• Filed: 03/28/2011
• Published: 10/04/2012
• Est. Priority Date: 03/28/2011
• Status: Abandoned Application

• Current Assignee: Taejin Info Tech Company Limited
• Original Assignee: Taejin Info Tech Company Limited
• Inventors: Cho, Byungcheol, Kim, Moon J.
• Application Number:
  US13/073,006
• Publication Number:
  US 20120254501A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Embodiments of the present invention provide a semiconductor storage device (SSD) system architecture based on flash memory. Specifically, embodiments of this invention provide a set of SSD RAID controllers coupled to a system control board. A set of flash memory control units coupled to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units.

Claims

1. A semiconductor storage device (SSD) system architecture based on flash memory, comprising:

a set of SSD RAID controllers coupled to a system control board;

a fibre channel chip coupled to the system control board; and

a set of flash memory control units coupled to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units.

2. The system architecture of claim 1, the system control board comprising:

a chip; and

a processor coupled to the chip.

3. The system architecture of claim 2, wherein the chip is coupled to the processor using a QuickPath Interconnect (QPI) or HyperTransport (HT) interface.

4. The system architecture of claim 1, wherein each of the set of flash memory control units are coupled to each of the set of SSD RAID controllers using serial attached SCSI (SAS).

5. A method for providing an SSD system architecture based on flash memory, comprising:

coupling a set of SSD RAID controllers to a system control board;

coupling a fibre channel chip to the system control board; and

coupling a set of flash memory control units to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units.

6. The method of claim 5, the system control board comprising:

a chip; and

a processor coupled to the chip.

7. The method of claim 5, wherein the chip is coupled to the processor using a QuickPath Interconnect (QPI) or HypeTransport (HT) interface.

8. The method of claim 5, wherein each of the set of flash memory control units are coupled to each of the set of SSD RAID controllers using serial attached SCSI (SAS).

9. An SSD system architecture based on flash memory, comprising:

a chip;

a processor coupled to the chip;

a main RAID controller coupled to the chip;

a set of SSD RAID controllers coupled to the main RAID controller; and

a set of flash memory control units coupled to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units.

10. The system architecture of claim 9, wherein the chip is coupled to the processor using a QPI or HT interface.

11. system architecture of claim 9, wherein each of the set of flash memory control units are coupled to each of the set of SSD RAID controllers using serial attached SCSI (SAS).

12. A method for providing an SSD system architecture based on flash, comprising:

coupling a processor coupled to a chip;

coupling a main RAID controller coupled to the chip;

coupling a set of SSD RAID controllers to the main RAID controller; and

coupling a set of flash memory control units to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units.

13. The method of claim 12, wherein the chip is coupled to the processor using a QPI or HT interface.

14. The method of claim 12, wherein each of the set of flash memory control units are coupled to each of the set of SSD RAID controllers using serial attached SCSI (SAS).

15. An SSD multi-level RAID system architecture based on flash memory, comprising:

a main RAID controller coupled to a system control board;

a set of flash memory RAID subcontrollers coupled to the main RAID controller; and

a set of flash memory RAID control blocks coupled to each of the set of flash memory RAID subcontrollers, each of the set of flash memory RAID control blocks comprising a set of flash memory units.

16. The system architecture of claim 15, the system control board comprising:

a chip;

a high-speed data controller coupled to the chip;

a low-speed data controller coupled to the chip;

a fibre channel chip coupled to the chip;

a processor coupled to the chip; and

cache memory coupled to the processor.

17. The system architecture of claim 15, the main RAID controller comprising:

a high-speed data controller; and

a low-speed data controller.

18. The system architecture of claim 15, each of the set of flash memory RAID control blocks further comprising:

a hot spare disk coupled to the set of flash memory units;

a RAID controller coupled to the set of flash memory units;

a RAID fail component coupled to the RAID controller; and

a data backup component coupled to the RAID controller.

19. The system architecture of claim 18, the RAID controller comprising a PCI-Express RAID controller.

20. An SSD multi-level RAID system architecture based on flash memory, comprising:

a main RAID controller coupled to a system control board;

a set of flash memory RAID subcontrollers coupled to the main RAID controller; and

a set of flash memory RAID control blocks coupled to each of the set of flash memory RAID subcontrollers, each of the set of flash memory RAID control blocks comprising a set of flash memory units and a PCI-Express RAID controller.

21. The system architecture of claim 20, the system control board comprising:

a chip;

a high-speed data controller coupled to the chip;

a low-speed data controller coupled to the chip;

a fibre channel chip coupled to the chip;

a processor coupled to the chip; and

cache memory coupled to the processor.

22. The system architecture of claim 20, the main RAID controller comprising:

a high-speed data controller; and

a low-speed data controller.

23. The system architecture of claim 20, each of the set of flash memory RAID control blocks further comprising:

a hot spare disk coupled to the set of flash memory units;

a RAID fail component coupled to the RAID controller; and

a data backup component coupled to the RAID controller.

24. A method for providing an SSD multi-level RAID system architecture based on flash memory, comprising:

coupling a main RAID controller to a system control board;

coupling a set of flash memory RAID subcontrollers to the main RAID controller; and

coupling a set of flash memory RAID control blocks to each of the set of flash memory RAID subcontrollers, each of the set of flash memory RAID control blocks comprising a set of flash memory units.

25. The method of claim 24, the system control board comprising:

a chip;

a high-speed data controller coupled to the chip;

a low-speed data controller coupled to the chip;

a fibre channel chip coupled to the chip;

a processor coupled to the chip; and

cache memory coupled to the processor.

26. The method of claim 24, the main RAID controller comprising:

a high-speed data controller; and

a low-speed data controller.

27. The method of claim 24, each of the set of flash memory RAID control blocks further comprising:

a hot spare disk coupled to the set of flash memory units;

a PCI-Express RAID controller coupled to the set of flash memory units;

a RAID fail component coupled to the RAID controller; and

a data backup component coupled to the RAID controller.