MULTI-LAYER MEMORY SYSTEM

• US 20120254574A1
• Filed: 03/31/2011
• Published: 10/04/2012
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sinclair, Alan Welsh, Wright, Barry, Thomas, Nicholas James
• Granted Patent: US 8,537,613 B2
• Time in Patent Office: Days
• US Class Current: 711/165
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices

Abstract

A multi-later memory and method for operation is disclosed. The memory includes three or more layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer. The method may include the steps of directing host data directly into a first or second layer of the multi-layer memory upon receipt depending on a condition of the data. The method may also include copying data within a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer, as well as transferring data from one layer to the next higher bit per cell layer when layer transfer criteria are met.

Claims

1. A mass storage memory system, comprising:

an interface adapted to receive data from a host system;

a plurality of memory layers, the plurality of memory layers comprising;

a first memory layer having non-volatile memory cells comprising a first bit per cell storage capacity;

a second memory layer having non-volatile memory cells comprising a second bit per cell storage capacity, the second bit per cell storage capacity being greater than the first bit per cell storage capacity; and

a third memory layer having non-volatile memory cells comprising a third bit per cell storage capacity, the third bit per cell storage capacity being greater than the second bit per cell storage capacity;

and

a controller in communication with the interface and the plurality of memory layers, the controller configured to direct data received from the host to one or more of the plurality of layers, and to transfer data between the plurality of memory layers.

2. The memory system of claim 1, wherein the first memory layer and the second memory layer are disposed on a first die and the third memory layer is disposed on a second die.

3. The memory system of claim 1, wherein the plurality of memory layers are disposed on a same die.

4. The memory system of claim 1, wherein each of the plurality of memory layers is disposed on respective separate die.

5. The memory system of claim 1, wherein the first memory layer comprises single level cell (SLC) memory cells having a one bit per cell capacity.

6. The memory system of claim 5, wherein the controller is further configured to direct data received at the interface from the host to the first memory layer when the data received comprises random logical block addresses, and is configured to direct the data received at the interface from the host to the second memory layer when the data received comprises sequential logical block addresses.

7. The memory system of claim 5, wherein the controller is further configured to:

reclaim blocks of memory cells via a block reclaim process within the first memory layer when a number of free blocks in the first memory layer is below a minimum threshold.

8. The memory system of claim 7, wherein the controller is further configured to:

when the percentage of valid data in the first memory layer exceeds the first valid data threshold and when the number of free blocks of memory cells is below the minimum threshold, transfer valid data from a selected block in the first memory layer to the second memory layer.

9. The memory system of claim 8, wherein the selected block comprises a least recently programmed block of valid data.

10. The memory system of claim 8, wherein the selected block comprises a previously programmed block in the first memory layer having valid data of an oldest average age.

11. The memory system of claim 7, wherein to execute the block reclaim process in the first memory layer, the controller is configured to select a block in the first memory layer having a least amount of valid data, copy valid data from the selected block to a relocation block in the first memory layer and return the selected block to a free block pool in the first memory layer.

12. The memory system of claim 11, wherein the controller is configured to copy valid data to the relocation block sequentially from the selected block regardless of a host logical block address associated with the valid data in the selected block.

13. A mass storage memory system, comprising:

an interface adapted to receive data from a host system;

a plurality of memory layers, the plurality of memory layers comprising;

a first memory layer having non-volatile memory cells comprising a first bit per cell storage capacity;

a second memory layer having non-volatile memory cells comprising a second bit per cell storage capacity, the second bit per cell storage capacity being greater than the first bit per cell storage capacity; and

a third memory layer having non-volatile memory cells comprising a third bit per cell storage capacity, the third bit per cell storage capacity being greater than the second bit per cell storage capacity;

and

a controller in communication with the interface and the plurality of memory layers, the controller configured to;

direct data received at the interface from the host to the first memory layer;

move data from the first memory layer to the second memory layer when a number of free blocks in the first memory layer is below a first minimum threshold and upon detection of an amount of valid data in the first memory layer exceeding a first valid data threshold; and

move data from the second memory layer to the third memory layer when a number of free blocks in the second memory layer is below a second minimum threshold and upon detection of an amount of valid data in the second memory layer exceeding a second valid data threshold.

14. The memory system of claim 13, wherein the controller is further configured to:

reclaim blocks of memory cells in a first block reclaim process within the first memory layer when the number of free blocks in the first memory layer reaches the first minimum threshold;

reclaim blocks of memory cells in a second block reclaim process within the second memory layer when the number of free blocks in the second memory layer reaches the second minimum threshold; and

reclaim blocks of memory cells in a third block reclaim process within the third memory layer when a number of free blocks in the third memory layer reaches a third minimum threshold.

15. A method of managing data comprising:

in a memory system having an interface for receiving data from a host, a plurality of memory layers, and a controller in communication with the interface and the plurality of memory layers, the controller;

directing data received at the interface to a first memory layer of the plurality of layers, the first memory layer having non-volatile memory cells comprising a first bit per cell storage capacity;

moving data from the first memory layer to a second memory layer when a first criteria is met, the second memory layer having non-volatile memory cells comprising a second bit per cell storage capacity, the second bit per cell storage capacity being greater than the first bit per cell storage capacity; and

moving data from the second memory layer to a third memory layer when a second criteria is met, the third memory layer having non-volatile memory cells comprising a third bit per cell storage capacity, the third bit per cell storage capacity being greater than the second bit per cell storage capacity.

16. The method of claim 15, wherein directing data received at the interface to the first memory layer comprises only directing data associated with non-sequential host logical block addresses to the first memory layer, and wherein the method further comprises directing data received at the interface and associated with sequential host logical block addresses to the second memory layer.

17. The method of claim 15, wherein moving data from the first memory layer to the second memory layer when the first criteria is met comprises moving valid data from a least recently programmed block in the first memory layer.

18. The method of claim 17, wherein moving data from the second memory layer to the third memory layer when the second criteria is met comprises moving valid data from a least recently programmed block in the second memory layer.

19. The method of claim 15, wherein moving data from the first memory layer to the second memory layer when the first criteria is met comprises moving valid data from a previously programmed block in the first memory layer having valid data of an oldest average age.

20. The method of claim 19, wherein moving data from the second memory layer to the third memory layer when the second criteria is met comprises moving valid data from a previously programmed block in the first memory layer having valid data of an oldest average age.

21. The method of claim 15, wherein the first criteria comprises the first memory layer having less than a first minimum threshold of free blocks and at least a first threshold amount of valid data and the second criteria comprises the second memory layer having less than a second minimum threshold of free blocks and at least a second threshold amount of valid data, and the method further comprises:

reclaiming at least one block of memory cells in the first memory layer when the number of free blocks in the first memory layer is below a first minimum threshold and the first memory layer has less than the first threshold amount of data; and

reclaiming at least one block of memory cells in the second memory layer when the number of free blocks in the second memory layer is below a second minimum threshold and the second memory layer has less than the second threshold amount of data.

22. The method of claim 21 wherein:

reclaiming at least one block of memory cells in the first memory layer comprises selecting a block in the first memory layer having a least amount of valid data, copying valid data from the selected block to a relocation block in the first memory layer and returning the selected block to a free block pool in the first memory layer; and

reclaiming at least one block of memory cells in the second memory layer comprises selecting a block in the second memory layer having a least amount of valid data, copying valid data from the selected block to a relocation block in the second memory layer and returning the selected block to a free block pool in the second memory layer.

24. The method of claim 22, wherein for each respective memory layer the controller is configured to copy valid data to the relocation block in the respective memory layer sequentially from the selected block regardless of a host logical block address associated with the valid data in the selected block.

25. A method of managing data comprising:

in a memory system having an interface for receiving data from a host, a plurality of memory layers, and a controller in communication with the interface and the plurality of memory layers, the controller;

directing data received at the interface to a first memory layer of the plurality of layers, the first memory layer having non-volatile memory cells comprising a first bit per cell storage capacity;

moving less recently updated data from the first memory layer to a second memory layer, the second memory layer having non-volatile memory cells comprising a second bit per cell storage capacity, the second bit per cell storage capacity being greater than the first bit per cell storage capacity; and

moving least recently updated data from the second memory layer to a third memory layer, the third memory layer having non-volatile memory cells comprising a third bit per cell storage capacity, the third bit per cell storage capacity being greater than the second bit per cell storage capacity.