SYSTEMS, APPARATUSES, AND METHODS FOR STRIDE PATTERN GATHERING OF DATA ELEMENTS AND STRIDE PATTERN SCATTERING OF DATA ELEMENTS

• US 20120254591A1
• Filed: 04/01/2011
• Published: 10/04/2012
• Est. Priority Date: 04/01/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hughes, Christopher J., Sans, Roger Espasa, Toll, Bret, Valentine, Robert C., Girkar, Milind Baburao, Foryth, Andrew Thomas, Grochowski, Edward Thomas, Adrian, Jesus Corbal San, Hall, Jonathan Cannon
• Application Number:
  US13/078,891
• Publication Number:
  US 20120254591A1
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/3555 using scaling, e.g. multiplication of index
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags

Abstract

Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask.

Claims

1. A method of performing a gather stride instruction in a computer processor, comprising:

fetching the gather stride instruction, wherein the gather stride instruction includes a destination register operand, a writemask, and memory source addressing information including scale, base, and stride values;

decoding the fetched gather stride instruction;

executing the fetched gather stride instruction to conditionally store strided data elements from memory into the destination register according to at least some of bit values of the writemask.

2. The method of claim 1, wherein the executing further comprises:

generating an address of a first data element in the memory, wherein the address is determined using the base value; and

determining if a first mask bit value of the writemask corresponding to the first data element in memory indicates that the first data element in memory is to be stored into the corresponding location in the destination register, wherein,

if the first mask bit value of the writemask corresponding to the first data element in memory does not indicate that the first data element is to be stored, leaving the data element in the corresponding location in the destination register unchanged, and

if the first mask bit value of the writemask corresponding to the first data element in memory does indicate that the first data element is to be stored, storing the first data element in the corresponding location in the destination register and clearing the first mask bit to indicate a successful storage.

3. The method of claim 2, wherein the first mask bit value is the least significant bit of the writemask and the first data element of the destination register is the least significant data element of the destination register.

4. The method of claim 2, wherein the executing further comprises:

determining that there is a fault with respect to the first data element in memory; and

halting the executing.

5. The method of claim 2, wherein the executing further comprises:

generating an address of a second data element in the memory, wherein the address is determined using the scale, base, and stride values, wherein the second data element is X data elements from the first data element and X is the stride value; and

determining if a second mask bit value of the writemask corresponding to the second data element in memory indicates that the second data element in memory is to be stored into the corresponding location in the destination register, wherein,

if the second mask bit value of the writemask corresponding to the second data element in memory does not indicate that the second data element is to be stored, leaving the second data element in the corresponding location in the destination register unchanged, and

if the second mask bit value of the writemask corresponding to the second data element in memory does indicate that the second data element is to be stored, storing the second data element in the corresponding location in the destination register and clearing the second mask bit to indicate a successful storage.

6. The method of claim 1, wherein a size of the data element in the destination register is 32 bits and the writemask is a dedicated 16-bit register.

7. The method of claim 1, wherein a size of the data element in the destination register is 64 bits and the writemask is a 16-bit register, wherein the eight least significant bits of the writemask are used to determine which data elements of the memory are to be stored into the destination register.

8. The method of claim 1, wherein a size of the data element in the destination register is 32 bits and the writemask is a vector register, wherein a sign bit for each data element of the writemask is the masking bit.

9. The method of claim 1, wherein any data element in memory that is stored into the destination register is upconverted prior its storage into the destination register.

10. A method of performing a scatter stride instruction in a computer processor, comprising:

fetching the scatter stride instruction, wherein the scatter stride instruction includes a source register operand, a writemask, and memory destination addressing information including scale, base, and stride values;

decoding the scatter stride instruction;

executing the scatter stride instruction to conditionally store data elements from the source register into strided positions of the memory according to at least some of bit values of the writemask.

11. The method of claim 10, wherein the executing further comprises:

generating an address of a first location in the memory, wherein the address is determined using the base value; and

determining if a first mask bit value of the writemask indicates that a first data element of the source register is to be stored into the memory at the generated address of the first location in memory, wherein,

if a first mask bit value of the writemask indicates that a first data element of the source register is not to be stored into the memory at the generated address of the first location in memory, leaving the data element at the generated address of the first location in memory unchanged, and

if a first mask bit value of the writemask indicates that a first data element of the source register is to be stored into the memory at the generated address of the first location in memory, storing the first data element of the source register at the generated address of the first location in memory and clearing the first mask bit to indicate a successful storage.

12. The method of claim 11, wherein the first mask bit value is the least significant bit of the writemask and the first data element is the least significant data element of the source register.

13. The method of claim 11, wherein the executing further comprises:

generating an address of a second location in the memory, wherein the address is determined using the scale, base, and stride values, wherein the address of the second location is X data elements from the first location and X is the stride value; and

determining if a second mask bit value of the writemask indicates that a second data element of the source register is to be stored into the memory at the generated address of the second location in memory, wherein,

if a second mask bit value of the writemask indicates that a second data element of the source register is not to be stored into the memory at the generated address of the second location in memory, leaving the data element at the generated address of the second location in memory unchanged, and

if a second mask bit value of the writemask indicates that a second data element of the source register is to be stored into the memory at the generated address of the second location in memory, storing the second data element of the source register at the generated address of the second location in memory and clearing the second mask bit to indicate a successful storage.

14. The method of claim 10, wherein a size of the data element in the source register is 32 bits and the writemask is a dedicated 16-bit register.

15. The method of claim 10, wherein a size of the data element in the source register is 64 bits and the writemask is a 16-bit register, wherein the eight least significant bits of the writemask are used to determine which data elements of the source register are to be stored into the memory.

16. The method of claim 10, wherein a size of the data element in the source register is 32 bits and the writemask is a vector register, wherein a sign bit for each data element of the writemask is the masking bit.

17. An apparatus comprising;

a hardware decoder to decode

a gather stride instruction, wherein the gather stride instruction includes a destination register operand, a writemask, and memory source addressing information including scale, base, and stride values, and

a scatter stride instruction, wherein the gather stride instruction includes a source register operand, a writemask, and memory destination addressing information including scale, base, and stride values;

execution logic to execute decoded gather stride and scatter stride instructions, wherein an execution of a decoded gather stride instruction to cause strided data elements from memory to be conditionally stored into the destination register according to at least some of bit values of the writemask of the gather stride instruction, and an execution of a decoded scatter gather stride to cause data elements to be conditionally stored into strided positions of the memory according to at least some of bit values of the writemask of the scatter stride instruction.

18. The apparatus of claim 17, wherein the execution logic comprises vector execution logic.

19. The apparatus of claim 17, wherein the writemask of the gather stride and/or scatter stride instruction is a dedicated 16-bit register.

20. The apparatus of claim 17, wherein the source register of the gather stride instruction is a 512-bit vector register.