SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION

• US 20120254592A1
• Filed: 04/01/2011
• Published: 10/04/2012
• Est. Priority Date: 04/01/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: San Adrian, Jesus Corbal, Sans, Roger Espasa, Valentine, Robert C., Wiedemeier, Jeffrey G., Samudrala, Sridhar, Girkar, Milind Baburao, Forsyth, Andrew Thomas, Lee, Victor W., Duran, Santiago Galan
• Application Number:
  US13/078,896
• Publication Number:
  US 20120254592A1
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.

Claims

1. A method of performing a compress instruction in a computer processor, comprising:

fetching the compress instruction, wherein the compress instruction includes a destination operand, a source operand, and a writemask operand;

decoding the fetched compress instruction;

executing the decoded compress instruction to select which data elements from the source are to be stored in the destination based on values of the writemask; and

storing the selected data elements of the source as sequentially packed data elements into the destination.

2. The method of claim 1, wherein the destination operand is memory and the source operand is a register.

3. The method of claim 1, wherein the source and destination operand are registers.

4. The method of claim 1, wherein the executing further comprises:

determining that a first bit position value of the writemask indicates that the corresponding first source data element should be stored into a location of the destination; and

storing the corresponding first source data element into the location of the destination.

5. The method of claim 1, wherein the executing further comprises:

determining that a first bit position value of the writemask indicates that the corresponding first source data element should not be stored into a location of the destination; and

evaluating a second bit position value of the writemask without storing the first source data element into a location of the destination.

6. The method of claim 1, wherein each source data element to be stored into the destination is first placed into a stream and the stream is stored into the destination.

7. The method of claim 1, further comprising:

downconverting the data elements to be stored into the destination prior to storing them into the destination.

8. The method of claim 7, wherein the data elements are downconverted from 32-bit values to 16-bit values.

14. The method of claim 1, wherein each source data element to be stored into the destination is first placed into a stream and the stream is stored into the destination.

15. The method of claim 1, further comprising:

upconverting the data elements to be stored into the destination prior to storing them into the destination.

16. The method of claim 7, wherein the data elements are upconverted from 16-bit values to 32-bit values.

9. A method of performing an expand instruction in a computer processor, comprising:

fetching the expand instruction, wherein the expand instruction includes a destination operand, a source operand, and a writemask operand;

decoding the expand compress instruction;

executing the expand compress instruction to select which elements from the source are to be sparsely stored in the destination based on values of the writemask; and

storing each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.

10. The method of claim 9, wherein the destination operand is a register and the source operand is memory.

11. The method of claim 9, wherein the source and destination operand are registers.

12. The method of claim 9, wherein the executing further comprises:

determining that a first bit position value of the writemask indicates that the corresponding first source data element should be stored into a corresponding location of the destination; and

storing the corresponding first source data element into the corresponding location of the destination.

13. The method of claim 9, wherein the executing further comprises:

determining that a first bit position value of the writemask indicates that the corresponding first source data element should not be stored into a corresponding location of the destination; and

evaluating a second bit position value of the writemask without storing the first source data element into a corresponding location of the destination.

17. An apparatus comprising;

a hardware decoder to decode an expand instruction and/or a compress instruction, wherein the expand instruction includes a first writemask operand, a first destination operand, a first source operand and the compress instruction includes a second writemask operand, a second destination operand, a second source operand; and

execution logic to

execute a decoded expand instruction to select which elements from the source are to be sparsely stored in the destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored, and

execute a decoded compress instruction to select which data elements from the source are to be stored in the destination based on values of the writemask and store the selected data elements of the source as sequentially packed data elements into the destination.

18. The apparatus of claim 17, further comprising:

a 16-bit writemask register to store the first or second writemask; and

a first 512-bit register to store the selected data elements.

19. The apparatus of claim 18, further comprising:

a second 512-bit register to act as a source for the expand and compress instructions.

20. The apparatus of claim 17, wherein the data elements are upconverted from 16-bit values to 32-bit values during the execution of an expand instruction.