SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION
First Claim
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1. A method of performing a compress instruction in a computer processor, comprising:
- fetching the compress instruction, wherein the compress instruction includes a destination operand, a source operand, and a writemask operand;
decoding the fetched compress instruction;
executing the decoded compress instruction to select which data elements from the source are to be stored in the destination based on values of the writemask; and
storing the selected data elements of the source as sequentially packed data elements into the destination.
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Abstract
Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.
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Citations
20 Claims
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1. A method of performing a compress instruction in a computer processor, comprising:
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fetching the compress instruction, wherein the compress instruction includes a destination operand, a source operand, and a writemask operand; decoding the fetched compress instruction; executing the decoded compress instruction to select which data elements from the source are to be stored in the destination based on values of the writemask; and storing the selected data elements of the source as sequentially packed data elements into the destination. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 14, 15, 16)
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9. A method of performing an expand instruction in a computer processor, comprising:
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fetching the expand instruction, wherein the expand instruction includes a destination operand, a source operand, and a writemask operand; decoding the expand compress instruction; executing the expand compress instruction to select which elements from the source are to be sparsely stored in the destination based on values of the writemask; and storing each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored. - View Dependent Claims (10, 11, 12, 13)
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17. An apparatus comprising;
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a hardware decoder to decode an expand instruction and/or a compress instruction, wherein the expand instruction includes a first writemask operand, a first destination operand, a first source operand and the compress instruction includes a second writemask operand, a second destination operand, a second source operand; and execution logic to execute a decoded expand instruction to select which elements from the source are to be sparsely stored in the destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored, and execute a decoded compress instruction to select which data elements from the source are to be stored in the destination based on values of the writemask and store the selected data elements of the source as sequentially packed data elements into the destination. - View Dependent Claims (18, 19, 20)
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Specification