DYNAMIC READ CHANNEL CALIBRATION FOR NON-VOLATILE MEMORY DEVICES

• US 20120254699A1
• Filed: 04/01/2011
• Published: 10/04/2012
• Est. Priority Date: 04/01/2011
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: RUBY, PAUL D., Belgal, Hanmant P., Wakchaure, Yogesh B., Guo, Xin, Nelson, Scott E., Salmons, Svanhild M.
• Granted Patent: US 8,510,636 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/136 Reed-Muller [RM] codes
• CPC Class Codes: H03M 13/1505 Golay Codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation

Abstract

Embodiments of the invention describe a dynamic read reference voltage for use in reading data from non-volatile memory cells. In embodiments of the invention, the read reference voltage is calibrated as the non-volatile memory device is used. Embodiments of the invention may comprise of logic and or modules to read data from a plurality of non-volatile memory cells using a first read reference voltage level (e.g., an initial read reference voltage level whose value is determined by the non-volatile device manufacturer). An Error Checking and Correction (ECC) algorithm is performed to identify whether errors exist in the data as read using the first read reference voltage level. If errors in the data as read are identified, a pre-determined value is retrieved to adjust the first read reference voltage level to a second read reference voltage level.

Claims

1. A method comprising:

reading data from a plurality of flash memory cells using a first read reference voltage level;

performing an error checking and correction (ECC) algorithm on the data to identify errors in the data; and

in response to identifying errors in the data, retrieving a stored value to adjust the first read reference voltage level to a second read reference voltage level.

2. The method of claim 1, wherein errors identified via the ECC algorithm comprise uncorrectable errors, the method further comprising:

re-reading the data from the plurality of flash memory cells using the second read reference voltage level;

performing the ECC algorithm on the re-read data to identify errors in the re-read data; and

in response to identifying uncorrectable errors in the re-read data, retrieving a third stored value to adjust the second read reference voltage level to a third read reference voltage level.

3. The method of claim 2, wherein the retrieved stored value and the second retrieved stored value comprise complementary offsets to the first read reference voltage level.

4. The method of claim 1, wherein errors identified via the ECC algorithm comprise correctable errors, the method further comprising:

determining a memory cell configured state corresponding to the most errors identified and corrected via the ECC algorithm, wherein retrieving the stored value to adjust the first read reference voltage level to the second read reference voltage level is based, at least in part, on the determined memory cell configured state.

5. The method of claim 1, wherein the stored value to adjust the first read reference voltage level to the second read reference voltage level is included in a look-up table (LUT).

6. The method of claim 1, further comprising persisting the second read reference voltage level to use with subsequent data reads to the plurality of flash memory cells.

7. An article of manufacture comprising a non-transitory machine-readable storage medium that provides instructions that, if executed by the machine, will cause the machine to perform operations comprising:

reading data from a plurality of flash memory cells using a first read reference voltage level;

performing an error checking and correction (ECC) algorithm on the data to identify errors in the data; and

in response to identifying errors in the data, retrieving a stored value to adjust the first read reference voltage level to a second read reference voltage level.

8. The article of manufacture of claim 7, wherein errors identified via the ECC algorithm comprise uncorrectable errors, the machine to perform operations further comprising:

re-reading the data from the plurality of flash memory cells using the second read reference voltage level;

performing the ECC algorithm on the re-read data to identify errors in the re-read data; and

in response to identifying uncorrectable errors in the re-read data, retrieving a third stored value to adjust the second read reference voltage level to a third read reference voltage level.

9. The article of manufacture of claim 8, wherein the retrieved stored value and the second retrieved stored value comprise complementary offsets to the first read reference voltage level.

10. The article of manufacture of claim 7, wherein errors identified via the ECC algorithm comprise correctable errors, the machine to perform operations further comprising:

determining a memory cell configured state corresponding to the most errors identified and corrected via the ECC algorithm, wherein retrieving the stored value to adjust the first read reference voltage level to the second read reference voltage level is based, at least in part, on the determined memory cell configured state.

11. The article of manufacture of claim 7, wherein the stored value to adjust the first read reference voltage level to the second read reference voltage level is included in a look-up table (LUT).

12. The article of manufacture of claim 7, further comprising persisting the second read reference voltage level to use with subsequent data reads to the plurality of flash memory cells.

13. A system comprising:

a flash memory device; and

a flash memory controller to

read data from a plurality of flash memory cells using a first read reference voltage level,

perform an error checking and correction (ECC) algorithm on the data to identify errors in the data, and

in response to identifying errors in the data, retrieve a stored value to adjust the first read reference voltage level to a second read reference voltage level.

14. The system of claim 13, wherein errors identified via the ECC algorithm comprise uncorrectable errors, the flash memory unit to further:

re-read the data from the plurality of flash memory cells using the second read reference voltage level;

perform the ECC algorithm on the re-read data to identify errors in the re-read data; and

in response to identifying uncorrectable errors in the re-read data, retrieve a third stored value to adjust the second read reference voltage level to a third read reference voltage level.

15. The system of claim 14, wherein the retrieved stored value and the second retrieved stored value comprise complementary offsets to the first read reference voltage level.

16. The system of claim 13, wherein errors identified via the ECC algorithm comprise correctable errors, the flash memory unit to further:

determine a memory cell configured state corresponding to the most errors identified and corrected via the ECC algorithm, wherein retrieving the stored value to adjust the first read reference voltage level to the second read reference voltage level is based, at least in part, on the determined memory cell configured state.

17. The system of claim 13 further comprising a look-up table (LUT), wherein the stored value to adjust the first read reference voltage level to the second read reference voltage level is included in the LUT.

18. The system of claim 13, the flash memory controller to further persist the second read reference voltage level to use with subsequent data reads to the plurality of flash memory cells.

19. The system of claim 13, further comprising:

an antenna; and

radio frequency circuitry coupled to the antenna to receive signal data to be stored on the flash memory device.