Integration of Lithography Apparatus and Mask Optimization Process with Multiple Patterning Process

• US 20120254813A1
• Filed: 04/04/2012
• Published: 10/04/2012
• Est. Priority Date: 04/04/2011
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Chen, Luoqi, Ye, Jun, Chen, Hong
• Granted Patent: US 8,819,601 B2
• Time in Patent Office: Days
• US Class Current: 716/54
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70508 Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
• CPC Class Codes: G03F 7/707 Chucks, e.g. chucking or un-chucking operations or structural details
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow.

Claims

1. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process.

2. The method of claim 1, wherein the splitting step comprises rule-based splitting, algorithm based splitting, or a combination of rule-based and algorithm-based splitting.

3. The method of claim 1, wherein the splitting and co-optimization are performed sequentially, in parallel, alternatively, or iteratively.

4. The method of claim 1, wherein the co-optimization-aware splitting step uses diffraction signature analysis to select the plurality of sub-patterns from a set of possible sub-patterns into which the pattern can be split, such that the desired imaging result is obtained.

5. The method of claim 1, wherein the co-optimization-aware splitting step uses two-dimensional pattern clustering in spatial domain to select the plurality of sub-patterns from a set of possible sub-patterns into which the pattern can be split, such that the desired imaging result is obtained.

6. The method of claim 1, wherein the co-optimization-aware splitting step uses one or both of frequency information and local spatial information of the pattern to select the plurality of sub-patterns from a set of possible sub-patterns into which the pattern can be split, such that the desired imaging result is obtained.

7. The method of claim 1, wherein the sub-patterns are sequentially imaged on the substrate while being combined on the single layer of the substrate.

8. The method of claim 1, wherein the desired imaging result is associated with a predefined process window for the selected plurality of sub-patterns.

9. The method of claim 1, wherein the optical setting of the lithography apparatus include one or more of:

setting and characteristics of an illumination source;

setting and characteristics of a projection optics system; and

, combined setting and characteristics of an illumination source and a projection optics system.

10. The method of claim 1, wherein a pattern selection method is used to select a representative smaller set of portions of design layout containing the patterns from a relatively larger set, wherein the representative smaller set adequately covers characteristic pattern features of the relatively larger set, such that the co-optimization process is expedited.

11. The method of claim 1, wherein known optical setting is used to generate rules for splitting the pattern, such that each of the plurality of sub-patterns contain features that are configured to be within a resolution limit of the lithography apparatus.

12. The method of claim 1, wherein optical proximity correction (OPC) is performed to further optimize the sub-patterns after optical settings are fixed as a result of the co-optimization.

13. The method of claim 12, wherein the OPC is performed for full-chip optimization.

14. The method of claim 1, wherein hot spots and warm spots are identified during a verification process that follows at least one iterative cycle of co-optimization.

15. The method of claim 14, wherein the identified hot spots and warm spots are fed back into a pattern-splitting algorithm used in the splitting step.

16. The method of claim 14, wherein the identified hot spots and warm spots are fed back into a pattern-selection algorithm that selects a representative smaller set of portions of design layout containing the patterns from a relatively larger set, wherein the representative smaller set adequately covers characteristic pattern features of the relatively larger set, such that the subsequent co-optimization process is expedited.

17. A computer program product comprising one or more computer-readable storage media having computer-executable instructions for causing a computer to select test patterns for calibrating a computational lithography model, the instructions causing the computer to perform the method of claim 1.