TRANSISTOR AND DISPLAY DEVICE

• US 20120256179A1
• Filed: 06/20/2012
• Published: 10/11/2012
• Est. Priority Date: 09/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, SAKAKURA, Masayuki, WATANABE, Ryosuke, SAKATA, Junichiro, AKIMOTO, Kengo, MIYANAGA, Akiharu, HIROHASHI, Takuya, KISHIDA, Hideyuki
• Granted Patent: US 9,935,202 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

Claims

1. A transistor comprising:

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including a channel region; and

an oxide insulating layer in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer is located between the gate insulating layer and the oxide insulating layer,

wherein the oxide semiconductor layer includes a first metal, a second metal, and a third metal,

wherein the first metal is indium, the second metal is zinc, and the third metal is a different metal from indium and zinc, and

wherein at least part of the channel region includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer.

2. The transistor according to claim 1, wherein the oxide semiconductor layer is formed over the gate electrode layer.

3. The transistor according to claim 1, wherein the part of the channel region includes a superficial portion of the oxide semiconductor layer.

4. The transistor according to claim 1, wherein a size of the crystals is 20 nm or less in a direction along a short axis direction.

5. The transistor according to claim 1, wherein the oxide semiconductor layer includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer throughout a thickness of the oxide semiconductor layer.

6. The transistor according to claim 1, wherein the crystals are microcrystals.

7. The transistor according to claim 1, wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

8. The transistor according to claim 1, wherein the oxide semiconductor layer is a laminate layer.

9. The transistor according to claim 1, further comprising a source electrode and a drain electrode each adjacent to the oxide semiconductor layer,

wherein each of the source electrode and the drain electrode has a three-layer structure in which aluminum is sandwiched by titanium.

10. The transistor according to claim 1, wherein the third metal is gallium.

11. The transistor according to claim 1, wherein the third metal is selected from gallium, aluminum, manganese, cobalt, and tin.

12. A transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including a channel region;

a source electrode over the oxide semiconductor layer;

a drain electrode over the oxide semiconductor layer;

an oxide insulating layer in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer is located between the gate insulating layer and the oxide insulating layer,

wherein the oxide semiconductor layer includes a first metal, a second metal, and a third metal,

wherein the first metal is indium, the second metal is zinc, and the third metal is a different metal from indium and zinc, and

wherein at least part of the channel region includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer.

13. The transistor according to claim 12, wherein the part of the channel region includes a superficial portion of the oxide semiconductor layer.

14. The transistor according to claim 12, wherein a size of the crystals is 20 nm or less in a direction along a short axis direction.

15. The transistor according to claim 12, wherein the oxide semiconductor layer includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer throughout a thickness of the oxide semiconductor layer.

16. The transistor according to claim 12, wherein the crystals are microcrystals.

17. The transistor according to claim 12, wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

18. The transistor according to claim 12, wherein the oxide semiconductor layer is a laminate layer.

19. The transistor according to claim 12, wherein each of the source electrode and the drain electrode has a three-layer structure in which aluminum is sandwiched by titanium.

20. The transistor according to claim 12, wherein the third metal is gallium.

21. The transistor according to claim 12, wherein the third metal is selected from gallium, aluminum, manganese, cobalt, and tin.

22. A transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween, the oxide semiconductor layer including a channel region;

a source electrode over the oxide semiconductor layer;

a drain electrode over the oxide semiconductor layer;

an oxide insulating layer in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer is located between the gate insulating layer and the oxide insulating layer,

wherein the oxide semiconductor layer includes a first metal, a second metal, and a third metal,

wherein the first metal is indium, the second metal is zinc, and the third metal is a different metal from indium and zinc, and

wherein at least part of the channel region includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer,

wherein an entirety of the oxide semiconductor layer overlaps with the gate electrode layer.

23. The transistor according to claim 22, wherein the gate electrode layer extends beyond all outer edge of the oxide semiconductor layer.

24. The transistor according to claim 22, wherein the part of the channel region includes a superficial portion of the oxide semiconductor layer.

25. The transistor according to claim 22, wherein a size of the crystals is 20 nm or less in a direction along a short axis direction.

26. The transistor according to claim 22, wherein the oxide semiconductor layer includes crystals which are c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer throughout a thickness of the oxide semiconductor layer.

27. The transistor according to claim 22, wherein the crystals are microcrystals.

28. The transistor according to claim 22, wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

29. The transistor according to claim 22, wherein the oxide semiconductor layer is a laminate layer.

30. The transistor according to claim 22, wherein each of the source electrode and the drain electrode has a three-layer structure in which aluminum is sandwiched by titanium.

31. The transistor according to claim 22, wherein the third metal is gallium.

32. The transistor according to claim 22, wherein the third metal is selected from gallium, aluminum, manganese, cobalt, and tin.