TEST STRUCTURE FOR PARALLEL TEST IMPLEMENTED WITH ONE METAL LAYER

• US 20120256651A1
• Filed: 04/08/2011
• Published: 10/11/2012
• Est. Priority Date: 04/08/2011
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ketchen, Mark B., BHUSHAN, MANJUL
• Application Number:
  US13/082,934
• Publication Number:
  US 20120256651A1
• Time in Patent Office: Days
• US Class Current: 324/756.01
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An integrated test circuit includes pads of a padset for testing multiple device under test units (MDUTs). The MDUTs each include devices under test (DUTs). A first integrated test circuit metal layer is patterned to connect the pads to N MDUTs such that a first set of pads are employed for enabling testing of each MDUT and a second set of pads are designated for testing individual DUTs associated with the enabled MDUTs such that N parallel tests may be concurrently performed.

Claims

1. An integrated test circuit, comprising:

a plurality of pads of a padset for testing multiple device under test units (MDUTs), the MDUTs each including a plurality of devices under test (DUTs); and

a first integrated test circuit metal layer patterned to connect the pads to N MDUTs such that a first set of the plurality of pads are employed for enabling testing of each MDUT and a second set of the plurality of pads are designated for testing individual DUTs associated with the enabled MDUTs such that N parallel tests may be concurrently performed.

2. The circuit as recited in claim 1, wherein the DUTs include transistors and the MDUT includes a plurality of DUTs connected in parallel.

3. The circuit as recited in claim 2, wherein the first set of the plurality of pads includes connections to a source pad and a drain pad for each MDUT, where the source pad and the drain pad are common for all DUTs of that MDUT.

4. The circuit as recited in claim 2, wherein the second set of the plurality of pads includes a connection to a gate pad for each DUT, the second set of the plurality of pads for testing individual DUTs for each corresponding MDUT.

5. The circuit as recited in claim 1, wherein a number of DUTs varies with a square of a number of pads.

6. The circuit as recited in claim 1, wherein the first integrated test circuit metal layer corresponds to a first metal layer of an integrated circuit process for an integrated circuit device being tested.

7. The circuit as recited in claim 1, wherein the DUT includes a circuit having one or more components.

8. The circuit as recited in claim 7, wherein the circuit includes components for testing contact resistance.

9. A system for testing integrated circuits, comprising:

a plurality of pads of a padset for testing N multiple device under test units (MDUTs), the MDUTs each including a plurality of devices under test (DUTs);

parallel wiring formed in a first metal layer and configured to selectively enable each MDUT through a first set of the plurality of pads, the parallel wiring further configured to enable individual DUT tests through a second set of the plurality of pads; and

a parallel tester configured to generate signals on the padset such that in conjunction with the parallel wiring, N parallel tests may be concurrently performed.

10. The system as recited in claim 9, wherein the DUT includes a transistor and the MDUT includes a plurality of DUTs connected in parallel.

11. The system as recited in claim 10, wherein the first set of the plurality of pads includes connections to a source pad and a drain pad for each MDUT, where the source pad and the drain pad are common for all DUTs of that MDUT.

12. The system as recited in claim 10, wherein the second set of the plurality of pads includes a connection to a gate pad for each DUT, the second set of the plurality of pads for testing individual DUTs for each corresponding MDUT.

13. The system as recited in claim 9, wherein a number of DUTs varies with a square of a number of pads.

14. The system as recited in claim 9, wherein the first metal layer corresponds to a first metal layer of an integrated circuit process for an integrated circuit device being tested.

15. The system as recited in claim 9, wherein the DUT includes a circuit having one or more components.

16. The system as recited in claim 15, wherein the circuit includes components for testing contact resistance.

17. The system as recited in claim 9, wherein the parallel tester generates signals for controlling pads not being tested.

18. A method for testing a test structure, comprising:

contacting a plurality of pads of a padset for testing multiple device under test units (MDUTs), the MDUTs each including a plurality of devices under test DUTs;

generating signals to a first integrated test circuit metal layer patterned to connect the pads to test N MDUTs such that a first set of the plurality of pads are employed for enabling testing of each MDUT and a second set of the plurality of pads are designated for testing individual DUTs associated with the enabled MDUTs; and

concurrently performing N parallel tests to test the DUTs.

19. The method as recited in claim 18, wherein the DUT includes a transistor and the MDUT includes a plurality of DUTs connected in parallel, the method further comprising enabling testing of each MDUT by generating signals on the first set of the plurality of pads to make connections to a source pad and a drain pad for that MDUT, the source pad and the drain pad being commonly connected to all DUTs of that MDUT.

20. The method as recited in claim 18, wherein the DUT includes a transistor and the MDUT includes a plurality of DUTs connected in parallel, the method further comprising enabling testing of the DUTs on an MDUT by generating signals on the second set of the plurality of pads to make a connection to a gate pad for each DUT, to test individual DUTs for each corresponding MDUT.

21. The method as recited in claim 18, wherein the first integrated test circuit metal layer is formed and patterned with a first metal layer during an integrated circuit process for an integrated circuit device for which the test structure is provided.

22. The method as recited in claim 18, wherein the DUT includes a circuit having one or more components, the method further comprising testing the one or more components.

23. The method as recited in claim 18, further comprising forming the test structure in a kerf region of a wafer.