PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES

• US 20120256653A1
• Filed: 04/06/2011
• Published: 10/11/2012
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cordero, Edgar R., Tremaine, Robert B.
• Granted Patent: US 8,493,089 B2
• Time in Patent Office: Days
• US Class Current: 326/16
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A configurable die stack arrangement including a first configurable integrated circuit die located on a first substrate. The first configurable integrated circuit die includes a first array and a first configuration memory management circuit that includes an interface to the first array. The first array includes a first logic element and a first configuration memory. The configurable die stack arrangement also includes a second configurable integrated circuit die located on a second substrate that is different than the first substrate. The second configurable integrated circuit die includes a second array and a second configuration memory management circuit that includes an interface to the second array. The second array includes a second logic element and a second configuration memory. A signal is coupled to the first configuration management circuit and to the second configuration management circuit, and the first configuration memory management circuit includes circuitry to control the signal.

Claims

1. A configurable die stack arrangement comprising:

a first configurable integrated circuit die located on a first substrate, the first configurable integrated circuit die comprising;

a first array comprising;

a first logic element; and

a first configuration memory; and

a first configuration memory management circuit comprising an interface to the first array;

a second configurable integrated circuit die located on a second substrate, the second substrate different than the first substrate, the second configurable integrated circuit die comprising;

a second array comprising;

a second logic element; and

a second configuration memory; and

a second configuration memory management circuit comprising an interface to the second array; and

a signal coupled to both the first configuration memory management circuit and the second configuration memory management circuit, wherein the first configuration memory management circuit further comprises a control circuit to control the signal.

2. The configurable die stack arrangement of claim 1, wherein the first configuration memory management circuit is configured to:

receive configuration memory data;

transmit a first portion of the received configuration memory data to the first configuration memory, the first portion of the received configuration memory data utilized by the first configuration memory to configure the first logic element; and

transmit, via the signal, a second portion of the received configuration memory data to the second configuration memory management circuit.

3. The configurable die stack arrangement of claim 1, wherein an output of the first configuration memory is coupled to an input of the second logic element, and the configurable die stack arrangement is configured such that data transmitted from the output of the first configuration memory to the input of the second logic element is time domain multiplexed and in high speed bursts.

4. The configurable die stack arrangement of claim 1, wherein an output of the first configuration memory is coupled to an input of the second logic element, and the configurable die stack arrangement is configured such that data transmitted from the output of the first configuration memory to the input of the second logic element is compressed at the first configurable integrated circuit die prior to being transmitted and decompressed at the second configurable integrated circuit die upon receipt of the data by the second configurable integrated circuit die.

5. The configurable die stack arrangement of claim 1, wherein an output of the second configuration memory is coupled to an input of the first logic element.

6. The configurable die stack arrangement of claim 1, wherein the first configuration memory management circuit further comprises an error detection and correction circuit to detect and correct errors in configuration memory data received via a first input.

7. The configurable die stack arrangement of claim 6, wherein the first configuration memory management circuit further comprises a means to disable the error detection and correction circuit to facilitate loading error data for testing fault tolerance of the first logic element.

8. The configurable die stack arrangement of claim 1, wherein the first configuration memory management circuit further comprises an integrity check circuit to perform an integrity check of data stored in the first configuration memory and a means to control a rate of the integrity check.

9. The configurable die stack arrangement of claim 8, wherein the first configuration memory management circuit further comprises a means to control a range of the integrity check at the rate of the integrity check.

10. The configurable die stack arrangement of claim 1, wherein the first configuration memory management circuit further comprises embedded dynamic random access memory (EDRAM).

11. The configurable die stack arrangement of claim 10, wherein the EDRAM includes a memory refresh synchronization circuit to align a refresh within a user clock period.

12. The configurable die stack arrangement of claim 1, wherein the second configurable integrated circuit die further comprises means to disable the interface to the second array, thereby allowing the second integrated circuit die to ignore data received from the first configuration memory management circuit.

13. The configurable die stack arrangement of claim 1, wherein the first logic element is a look-up-table (LUT).

14. A method of configuring a plurality of configurable integrated circuit dies, the method comprising:

receiving a configuration data stream at a die stack, the configuration data stream comprising configuration memory data for a plurality of configuration memories and logic devices located on dies in the die stack, at least two of the dies in the die stack located on different substrates; and

performing for each die in the die stack;

receiving the configuration memory data for the die;

storing the configuration memory data for the die in a configuration memory on the die;

determining whether the configuration data stream includes configuration memory data for an additional die in the die stack; and

transmitting the configuration data stream to the additional die in the die stack responsive to the configuration data stream including configuration memory data for the additional die in the die stack.

15. The method of claim 14, further comprising configuring the plurality of logic devices responsive to contents of the plurality of configuration memories.

16. The method of claim 14, wherein the transmitting between dies is performed using through substrate vias (TSVs).

17. The method of claim 16, further comprising compressing the configuration data stream prior to the transmitting.

18. The method of claim 16, further comprising performing error detection and correction on the configuration data stream.

19. A computer program product for configuring a plurality of configurable integrated circuit dies, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

receiving a configuration data stream at a die stack, the configuration data stream comprising configuration memory data for a plurality of configuration memories and logic devices located on dies in the die stack, at least two of the dies in the die stack located on different substrates; and

performing for each die in the die stack;

receiving the configuration memory data for the die, the die located on a first substrate;

storing the configuration memory data for the die in a configuration memory on the die;

determining whether the configuration data stream includes configuration memory data for an additional die in the die stack, the additional die located on a second substrate different than the first substrate; and

transmitting the configuration data stream to the additional die in the die stack responsive to the configuration data stream including configuration memory data for the additional die in the die stack.

20. The computer program product of claim 19, wherein the method further comprises configuring the plurality of logic devices responsive to contents of the plurality of configuration memories.

21. The computer program product of claim 19, wherein the method further comprises compressing the configuration data stream prior to the transmitting.

22. The computer program product of claim 19, wherein the method further comprises performing error detection and correction on the configuration data stream.

23. A method of testing configuration data for configurable integrated circuit dies, the method comprising:

receiving a test configuration data stream at a die stack, the test configuration data stream comprising configuration memory data for a plurality of configuration memories and logic devices located on dies in the die stack, at least two of the dies in the die stack located on different substrates, the configuration memory data comprising at least one faulty bit;

placing the die stack in a test mode that disables error detection and correction of the configuration data stream; and

performing for each die in the die stack;

receiving the configuration memory data for the die;

storing the configuration memory data for the die in a configuration memory on the die;

determining whether the test configuration data stream includes configuration memory data for an additional die in the die stack; and

transmitting the test configuration data stream to the additional die in the die stack responsive to the test configuration data stream including configuration memory data for the additional die in the die stack.