HIGH VOLTAGE LATCHING AND DC RESTORATION ISOLATION AND LEVEL SHIFTING METHOD AND APPARATUS

• US 20120256656A1
• Filed: 06/21/2012
• Published: 10/11/2012
• Est. Priority Date: 09/15/2006
• Status: Active Grant

• Current Assignee: Texas Instruments Northern Virginia, Inc. (Texas Instruments, Inc.)
• Original Assignee: Texas Instruments Northern Virginia, Inc. (Texas Instruments, Inc.)
• Inventors: Stirk, Gary, Jiang, Jong-Dii, Houldsworth, John
• Granted Patent: US 8,717,063 B2
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: H02J 7/0013 acting upon several batteries simultaneously or sequentially H02J7/1423 takes precedence
• CPC Class Codes: H02J 7/0047 with monitoring or indicating devices or circuits

Abstract

A device and method for dc isolation and level shifting includes a driver circuit powered by a first voltage range, a capacitor connected to the driver circuit, and a latching circuit connected to the capacitor. The latching circuit is powered by a second voltage range and is configured to restore and/or minimize charge loss of the capacitor during a voltage transition at the capacitor. A device and method for analog isolation and measurement configured to measure an analog voltage at a second potential without requiring analog circuits at the second potential.

Claims

1. A V-bus circuit, comprising:

a first level circuit;

a level shifter connected to the first level circuit;

a second level circuit connected to the level shifter; and

a capacitor connected to a terminal of the second level shifter,

wherein the level shifter is configured to control inputs of the first and second level circuits.

2. The V-bus circuit of claim 1, wherein the first level circuit comprises:

a port, a first logic gate which can produce a hard high, a second logic gate which can produce a hard low, a third logic gate which can produce a soft high and a fourth logic gate which can produce a soft low, the port being connected to an output of the first, second, third and fourth logic gates.

3. The V-bus circuit of claim 2, wherein when the port receives a logic level, one of the third or fourth logic gates provides soft reinforcement to the logic level at the port, and the first level circuit transfers the logic level to the level shifter.

4. The V-bus circuit of claim 2, wherein when a logic level is input to the level shifter, one of the first or second logic gates produces a hard level.

5. The V-bus circuit of claim 2, further comprises a port, the port being connected to one terminal of the capacitor.

6. The V-bus circuit of claim 5, wherein when the port receives a logic level, one of the third or fourth logic gates provides soft reinforcement to the logic level at the port, and the first level circuit transfers the logic level to the level shifter.

7. The V-bus circuit of claim 5, wherein when a logic level is input to the level shifter, one of the first or second logic gates sets the port to a logic hard level.

8. The V-bus circuit of claim 1, wherein the level shifter comprises:

a driver circuit powered by a first voltage range;

a capacitor connected to the driver circuit; and

a latching circuit connected to the capacitor, the latching circuit being powered by a second voltage range wherein the latching circuit is configured to restore and/or minimize charge loss of the capacitor during a voltage transition at the capacitor.

9. The V-bus circuit of claim 1, wherein the first level circuit is in a deep N-well region and the second level circuit is in a P-substrate.

10. The V-bus circuit of claim 1, wherein the first level circuit is in a P-substrate and the second level circuit is in a deep N-well region.