DESIGN, LAYOUT, AND MANUFACTURING TECHNIQUES FOR MULTIVARIANT INTEGRATED CIRCUITS

• US 20120258579A1
• Filed: 04/11/2011
• Published: 10/11/2012
• Est. Priority Date: 04/11/2011
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kelleher, Brian
• Granted Patent: US 8,701,057 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

Techniques for the integral design, layout, and manufacture of integrated circuits include designing an integrated circuit that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the integrated circuit. The layout includes primary scribe boundaries separating each set of the plurality of modular circuits of the first variant. The layout also includes secondary scribe boundaries separating the sub-set of the plurality of modular circuits of the second variant from the other modular circuits in the first variant. The layout further includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the integrated circuit is then started, up to but not including the one or more metallization layers to be fabricated last, according to the layout. A demand for each of the integrated circuit variants is predicted during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the integrated circuit is selected based upon the predicted demand. Fabrication then continues with the last one or more metallization layers of the integrated circuit according to the layout of the selected one or more variants of the integrated circuit. The wafer is then singulated into a plurality of integrated circuit die according to the layout of the selected one or more variants of the integrated circuit.

Claims

1. A method comprising:

designing an integrated circuit including a plurality of selectable groupings of a modular circuit;

laying out the integrated circuit including scribe boundaries between particular groupings of the modular circuit, and routing the interconnects and vias between modular circuits that cross the scribe boundaries between the particular groupings of the modular circuit in the last one or more metallization layers to be fabricated;

fabricating the integrated circuit on one or more wafers accordingly to the layout up to but not including the interconnects and vias;

predicting a demand for each of the plurality of selectable groupings of the modular circuit during fabrication of the integrated circuit up to but not including the interconnects and vias;

selecting one or more of the plurality of groupings of the modular circuit based upon the predicted demand;

fabricating the interconnects and vias of the integrated circuit according to the layout of the selected one or more groupings of the modular circuit; and

singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more groupings of the modular circuit.

2. The method according to claim 1, wherein the modular circuit comprises one or more processor cores and one or more associated peripheral circuits.

3. The method according to claim 1, wherein predicting the demand comprises a market analysis of each of the plurality of selectable groupings of the modular circuit.

4. The method according to claim 1, further comprising:

estimating a yield for each of the plurality of selectable groupings of the modular circuit during fabrication of the integrated circuit up to but not including the interconnects and vias; and

selecting the one or more of the plurality of groupings of the modular circuit further based upon the estimated yield.

5. The method according to claim 1, further comprising:

predicting an initial demand for each of the plurality of selectable groupings of the modular circuit before fabricating the integrated circuit up to but not including the interconnects and vias; and

fabricating the integrated circuit on one or more wafers according to the layout and the initial predicted demand up to but not including the interconnects and vias.

6. The method according to claim 1, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and a demand; and

designing the integrated circuit including the plurality of selectable groupings of a modular circuit based on the market analysis.

7. The method according to claim 1, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and a demand; and

laying out the integrated circuit based on the market analysis.

8. A method comprising:

designing an integrated circuit including a plurality of variants, wherein one integrated circuit variant includes a plurality of modular circuits communicatively coupled together and a second integrated circuit variant includes a sub-set of the plurality of modular circuits;

laying out the plurality of variants of the integrated circuit for wafer fabrication, wherein the layout includes primary scribe boundaries separating each set of the plurality of modular circuits of the first variant and secondary scribe boundaries separating the sub-set of the plurality of modular circuits of the second variant from the other modular circuits in the first variant, and wherein the layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last;

fabricating the integrated circuit on a wafer according to the layout up to but not including the one or more metallization layers to be fabricated last;

predicting a demand for each of the integrated circuit variants during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last;

selecting one or more of the plurality of variants of the integrated circuit based upon the predicted demand;

fabricating the last one or more metallization layers of the integrated circuit according to the layout of the selected one or more variants of the integrated circuit; and

singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more variants of the integrated circuit.

9. The method according to claim 8, wherein predicting the demand comprises a market analysis of the demand for each of the plurality of variants.

10. The method according to claim 8, further comprising:

estimating a yield for each of the plurality of variants during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last; and

selecting the one or more of the plurality of groupings of the modular circuit further based upon the estimated yield.

11. The method according to claim 8, further comprising:

predicting an initial demand for each of the plurality of variants before fabricating the integrated circuit up to but not including the one or more metallization layers to be fabricated last; and

fabricating the integrated circuit according to the layout and the initial predicted demand up to but not including the one or more metallization layers to be fabricated last.

12. The method according to claim 8, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and a demand; and

designing the integrated circuit including the plurality of variants based on the market analysis.

13. The method according to claim 8, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and a demand; and

laying out the plurality of variants of the integrated circuit based on the market analysis.

14. The method according to claim 8, further comprising:

packaging the plurality of integrated circuit die into integrated circuit chips of the selected one or more variants; and

shipping the integrated circuit chips of the selected one or more variants.

15. A method comprising:

designing a first set of one or more modular circuits and a second set of the one or more modular circuits, wherein the first set of modular circuits are adapted to separately implement a first one of a plurality of selectable integrated circuits and the second set of modular circuits are adapted to separately implement a second one of a plurality of selectable integrated circuits, or the first and second sets of the modular circuits are adapted to combine to implement a third one of a plurality of selectable integrated circuits;

laying out a plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits, wherein each instantiation of the first and second set of modular integrated circuits are separated from other instantiations by primary scribe boundaries, wherein the first set and second set of the modular circuits of each instantiation are separated by a secondary scribe boundary, and wherein interconnects and vias between the first set and second set of the modular circuits in each instantiation are laid out in one or more metallization layers to be fabricated last;

fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer according to the layout up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits in each instantiation;

predicting a demand for each of the first, second and third integrated circuits during fabrication of the plurality of instantiations of the first and second sets of modular circuits up to the one or more metallization layers including the interconnects and vias between the first and second sets of the modular circuits in each instantiation;

selectively fabricating the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits or not based upon the predicted demand for the first, second and third integrated circuits; and

selectively singulating the wafer into a first plurality of dice each including the first set of one or more modular circuits and a second plurality of dice each including the second set of one or more modular circuits along the primary and secondary scribe boundaries, or into a third plurality of die each including the first and second set of modular integrated circuits and the interconnects and vias along the primary scribe boundaries.

16. The method according to claim 15, further comprising:

estimating a yield for each of the selectable integrated circuits during fabrication of the integrated circuit up to but not including the interconnects and vias;

selectively fabricating the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits or not further based upon the estimated yield; and

selectively singulating the wafer into the first plurality of dice each and the second plurality of dice each along the primary and secondary scribe boundaries, or into the third plurality of die along the primary scribe boundaries further based upon the estimated yield.

17. The method according to claim 15, further comprising:

estimating an initial yield for each of the selectable integrated circuits prior to fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits;

designing the first set of one or more modular circuits and the second set of one or more modular circuits based on the initial estimated yield; and

laying out the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits based on the initial estimated yield.

18. The method according to claim 15, further comprising:

predicting an initial demand for each of the selectable integrated circuits prior to fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits; and

fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits according to the layout and the initial predicted demand.

19. The method according to claim 15, wherein the first set of one or more modular circuits includes a different number of modular circuits as the second set of one or more modular circuits.

20. The method according to claim 15, wherein the first set of one or more modular circuits includes a same number of modular circuits as the second set of one or more modular circuits.