DESIGN, LAYOUT, AND MANUFACTURING TECHNIQUES FOR MULTIVARIANT INTEGRATED CIRCUITS
First Claim
1. A method comprising:
- designing an integrated circuit including a plurality of selectable groupings of a modular circuit;
laying out the integrated circuit including scribe boundaries between particular groupings of the modular circuit, and routing the interconnects and vias between modular circuits that cross the scribe boundaries between the particular groupings of the modular circuit in the last one or more metallization layers to be fabricated;
fabricating the integrated circuit on one or more wafers accordingly to the layout up to but not including the interconnects and vias;
predicting a demand for each of the plurality of selectable groupings of the modular circuit during fabrication of the integrated circuit up to but not including the interconnects and vias;
selecting one or more of the plurality of groupings of the modular circuit based upon the predicted demand;
fabricating the interconnects and vias of the integrated circuit according to the layout of the selected one or more groupings of the modular circuit; and
singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more groupings of the modular circuit.
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Accused Products
Abstract
Techniques for the integral design, layout, and manufacture of integrated circuits include designing an integrated circuit that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the integrated circuit. The layout includes primary scribe boundaries separating each set of the plurality of modular circuits of the first variant. The layout also includes secondary scribe boundaries separating the sub-set of the plurality of modular circuits of the second variant from the other modular circuits in the first variant. The layout further includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the integrated circuit is then started, up to but not including the one or more metallization layers to be fabricated last, according to the layout. A demand for each of the integrated circuit variants is predicted during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the integrated circuit is selected based upon the predicted demand. Fabrication then continues with the last one or more metallization layers of the integrated circuit according to the layout of the selected one or more variants of the integrated circuit. The wafer is then singulated into a plurality of integrated circuit die according to the layout of the selected one or more variants of the integrated circuit.
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Citations
20 Claims
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1. A method comprising:
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designing an integrated circuit including a plurality of selectable groupings of a modular circuit; laying out the integrated circuit including scribe boundaries between particular groupings of the modular circuit, and routing the interconnects and vias between modular circuits that cross the scribe boundaries between the particular groupings of the modular circuit in the last one or more metallization layers to be fabricated; fabricating the integrated circuit on one or more wafers accordingly to the layout up to but not including the interconnects and vias; predicting a demand for each of the plurality of selectable groupings of the modular circuit during fabrication of the integrated circuit up to but not including the interconnects and vias; selecting one or more of the plurality of groupings of the modular circuit based upon the predicted demand; fabricating the interconnects and vias of the integrated circuit according to the layout of the selected one or more groupings of the modular circuit; and singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more groupings of the modular circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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designing an integrated circuit including a plurality of variants, wherein one integrated circuit variant includes a plurality of modular circuits communicatively coupled together and a second integrated circuit variant includes a sub-set of the plurality of modular circuits; laying out the plurality of variants of the integrated circuit for wafer fabrication, wherein the layout includes primary scribe boundaries separating each set of the plurality of modular circuits of the first variant and secondary scribe boundaries separating the sub-set of the plurality of modular circuits of the second variant from the other modular circuits in the first variant, and wherein the layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last; fabricating the integrated circuit on a wafer according to the layout up to but not including the one or more metallization layers to be fabricated last; predicting a demand for each of the integrated circuit variants during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last; selecting one or more of the plurality of variants of the integrated circuit based upon the predicted demand; fabricating the last one or more metallization layers of the integrated circuit according to the layout of the selected one or more variants of the integrated circuit; and singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more variants of the integrated circuit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method comprising:
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designing a first set of one or more modular circuits and a second set of the one or more modular circuits, wherein the first set of modular circuits are adapted to separately implement a first one of a plurality of selectable integrated circuits and the second set of modular circuits are adapted to separately implement a second one of a plurality of selectable integrated circuits, or the first and second sets of the modular circuits are adapted to combine to implement a third one of a plurality of selectable integrated circuits; laying out a plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits, wherein each instantiation of the first and second set of modular integrated circuits are separated from other instantiations by primary scribe boundaries, wherein the first set and second set of the modular circuits of each instantiation are separated by a secondary scribe boundary, and wherein interconnects and vias between the first set and second set of the modular circuits in each instantiation are laid out in one or more metallization layers to be fabricated last; fabricating the plurality of instantiations of the first set of one or more modular circuits and the second set of one or more modular circuits on a wafer according to the layout up to but not including the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits in each instantiation; predicting a demand for each of the first, second and third integrated circuits during fabrication of the plurality of instantiations of the first and second sets of modular circuits up to the one or more metallization layers including the interconnects and vias between the first and second sets of the modular circuits in each instantiation; selectively fabricating the one or more metallization layers including the interconnects and vias between the first set and second set of the modular circuits or not based upon the predicted demand for the first, second and third integrated circuits; and selectively singulating the wafer into a first plurality of dice each including the first set of one or more modular circuits and a second plurality of dice each including the second set of one or more modular circuits along the primary and secondary scribe boundaries, or into a third plurality of die each including the first and second set of modular integrated circuits and the interconnects and vias along the primary scribe boundaries. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification