SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS

• US 20120261689A1
• Filed: 04/13/2011
• Published: 10/18/2012
• Est. Priority Date: 04/13/2011
• Status: Abandoned Application

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Appelt, Bernd Karl, Rice, Richard Alan, Lee, Andrew T.W.
• Application Number:
  US13/086,280
• Publication Number:
  US 20120261689A1
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/12035 : Zener diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/54 : having a particular shape
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

The packages include a plurality of spaced conductive standoffs electrically coupling the semiconductor die to, variously, a substrate and bottom package contacts. The conductive standoffs may be pillars or posts. The substrate includes at least one electrically isolated portion, which has exposed sidewalls.

Claims

1. A semiconductor package, comprising:

a leadframe including an isolated block and at least one lead at a periphery of the package, the isolated block having a lateral surface, the lateral surface having a sloped upper portion and a sloped lower portion, wherein a junction of the sloped upper portion and the sloped lower portion defines an apex, the at least one lead having a lateral surface, the lateral surface having a sloped upper portion and a sloped lower portion, wherein a junction of the sloped upper portion and the sloped lower portion defines an apex;

a plurality of conductive standoffs coupled to an upper surface of the isolated block and the at least one lead;

a die coupled to the plurality of conductive standoffs with a space between the die and the isolated block; and

a package body at least partially encapsulating the die, the sloped upper portions of the isolated block, and the at least one lead, wherein the sloped lower portions of the isolated block and the at least one lead protrude from the package body.

2. The semiconductor package of claim 1, wherein the leadframe includes an opening surrounding the isolated block, the opening electrically isolating the isolated block from the balance of the substrate.

3. The semiconductor package of claim 1, wherein the package body contains thermally conductive particles.

4. The semiconductor package of claim 1, wherein the die is a light-emitting diode (LED) die.

5. The semiconductor package of claim 4, wherein the package body includes a lens portion over the die.

6. The semiconductor package of claim 1, wherein the leadframe is copper or a copper alloy, and upper and lower surfaces thereof comprise a nickel/gold layer.

7. The semiconductor package of claim 1, wherein the conductive standoffs are pillars.

8. A semiconductor package, comprising:

a leadframe including an isolated block and at least one lead at a periphery of the package, the isolated block having a lateral surface, the lateral surface having a sloped upper portion and a sloped lower portion, wherein a junction of the sloped upper portion and the sloped lower portion defines an apex, the at least one lead having a lateral surface, the lateral surface having a sloped upper portion and a sloped lower portion, wherein a junction of the sloped upper portion and the sloped lower portion defines an apex;

a die coupled to the isolated block and electrically connected to the at least one lead;

a first encapsulant encapsulating a portion of the die, the sloped upper surfaces of the isolated block, and the at least one lead, the sloped lower portions of the isolated block and the at least one lead protruding from the first encapsulant; and

a second encapsulant encapsulating a light emitting portion of the die, wherein the second encapsulant permits the passage of light.

9. The semiconductor package of claim 8, wherein the leadframe includes an opening defining an isolated block, the opening electrically isolating the isolated block from the balance of the substrate.

10. The semiconductor package of claim 8, wherein the first encapsulant contains thermally conductive particles.

11. The semiconductor package of claim 8, wherein the die is a light-emitting diode (LED) die.

12. The semiconductor package of claim 11, wherein the second encapsulant includes a lens portion over the die.

13. The semiconductor package of claim 8, wherein the leadframe is copper or a copper alloy, and upper and lower surfaces thereof comprise a nickel/gold layer.

14. The semiconductor package of claim 8, wherein the conductive standoffs are pillars.

15. A method of making a semiconductor package, the method comprising:

forming conductive layers on top and bottom surfaces of a substrate;

forming an opening in the substrate to thereby define an isolated block and a plurality of leads at a periphery of the package, the isolated block having a lateral surface with a sloped upper portion and a sloped lower portion, wherein a junction of the sloped upper portion and the sloped lower portion defines an apex, each of the leads having a lateral surface, the lateral surface having a sloped upper portion and a sloped lower portion, wherein a junction of the sloped upper portion and the sloped lower portion defines an apex;

forming a plurality of conductive standoffs on an upper surface of the isolated block and the leads;

coupling a die to the plurality of conductive standoffs with a space between the die and the isolated block; and

forming a package body coupled to the package such that the body at least partially encapsulates the die, the sloped upper portions of the isolated block, and the sloped upper portions of the leads, wherein the sloped lower portions of the isolated block and the leads protrude from the package body.

16. The method of claim 15, wherein forming the opening electrically isolates the isolated block from the balance of the substrate.

17. The method of claim 15, wherein the package body contains thermally conductive particles.

18. The method of claim 15, wherein the die is a light-emitting diode (LED) die.

19. The method of claim 18, further comprising forming a lens portion in the package body over the die.

20. The method of claim 15, wherein forming the conductive standoffs comprises forming pillars.