NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

• US 20120261736A1
• Filed: 07/04/2011
• Published: 10/18/2012
• Est. Priority Date: 04/18/2011
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Technology Corporation
• Inventors: Hsu, Cheng-Yuan, Li, Chun-Hsiao
• Granted Patent: US 8,421,141 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A non-volatile memory device includes a substrate, a gate stack, a selecting gate, an erasing gate, a source region, and a drain region. The gate stack on the substrate includes from bottom to top a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a spacer that is located between sidewalls of the control gate and the inter-gate dielectric layer. A side of the floating gate adjacent to the erasing gate has a warp-around profile and a sharp corner protruding from a vertical surface of the spacer. The selecting and erasing gates are respectively located at first and second sides of the substrate of the gate stack. The source region is located in the substrate under the erasing gate. The drain region is located in the substrate at a side of the selecting gate.

Claims

1. A non-volatile memory comprising:

a substrate;

a first gate stack located on the substrate;

a selecting gate located on the substrate at a first side of the first gate stack;

an erasing gate located on the substrate at a second side of the first gate stack;

a source region located in the substrate under the erasing gate;

a drain region located in the substrate at a side of the selecting gate;

a first dielectric layer located between the first gate stack and the erasing gate and between the first gate stack and the source region; and

a second dielectric layer located between the selecting gate and the substrate,

the first gate stack comprising;

a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate sequentially stacked from bottom to top; and

a spacer located on a sidewall of the control gate and a sidewall of the inter-gate dielectric layer,

wherein a side of the floating gate adjacent to the erasing gate has a warp-around profile and has a sharp corner, and the sharp corner protrudes from a vertical surface of the spacer.

2. The non-volatile memory as recited in claim 1, wherein the erasing gate has a recess profile corresponding to the sharp corner of the floating gate.

3. The non-volatile memory as recited in claim 1, wherein the first dielectric layer conformally covers a surface of the first gate stack and a surface of the source region.

4. The non-volatile memory as recited in claim 1, further comprising a buffer layer located between the spacer and the floating gate.

5. The non-volatile memory as recited in claim 1, wherein the first gate stack further comprises a cap layer located on the control gate.

6. The non-volatile memory as recited in claim 1, further comprising:

a second gate stack, a structure of the second gate stack and a structure of the first gate stack being the same, the second and first gate stacks constituting a gate stack set; and

another drain region located in the substrate at a side of the second gate stack.

7. A method of fabricating a non-volatile memory, comprising:

sequentially forming a tunneling dielectric layer and a first patterned conductive layer on a substrate;

sequentially stacking a patterned inter-gate dielectric layer and a second patterned conductive layer on a first surface of the first patterned conductive layer and exposing a second surface of the first patterned conductive layer, the second surface being adjacent to the first surface;

covering the substrate by a passivation layer and exposing a first sidewall of the first patterned conductive layer;

forming a recess on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner;

forming a source region in the substrate adjacent to the first sidewall of the first patterned conductive layer;

removing a portion of the passivation layer on the second surface, such that the sharp corner of the first patterned conductive layer is exposed; and

forming a drain region in the substrate outside a second sidewall of the first patterned conductive layer.

8. The method of fabricating the non-volatile memory as recited in claim 7, wherein the step of forming the passivation layer comprises:

forming a buffer layer on the second surface of the first patterned conductive layer; and

forming a spacer and a shielding layer on the buffer layer and the substrate at a first side of the second patterned conductive layer, wherein the spacer is located between the second patterned conductive layer and the shielding layer.

9. The method of fabricating the non-volatile memory as recited in claim 8, wherein the step of removing the portion of the passivation layer on the second surface comprises removing the shielding layer and the underlying buffer layer, so as to expose the sharp corner of the first patterned conductive layer.

10. The method of fabricating the non-volatile memory as recited in claim 8, wherein the step of forming the first patterned conductive layer, the patterned inter-gate dielectric layer, the second patterned conductive layer, the buffer layer, the spacer, and the shielding layer comprises:

forming a first conductive layer on the tunneling dielectric layer and exposing a portion of the tunneling dielectric layer;

forming the patterned inter-gate dielectric layer and the second patterned conductive layer on the first conductive layer;

removing a portion of the first conductive layer at the first side of the second patterned conductive layer;

forming a buffer material layer on the first conductive layer at a second side of the second patterned conductive layer;

forming the spacer and the shielding layer on a sidewall of the second patterned conductive layer, a sidewall of the patterned inter-gate dielectric layer, and the second sidewall of the first patterned conductive layer and exposing the buffer material layer at the second side of the second patterned conductive layer; and

removing the buffer material layer exposed by the shielding layer at the second side of the second patterned conductive layer and removing the first conductive layer located under the buffer material layer, the remaining first conductive layer being the first patterned conductive layer, the remaining buffer material layer being the buffer layer.

11. The method of fabricating the non-volatile memory as recited in claim 10, wherein a method of forming the shielding layer comprises:

forming a shielding material layer on the substrate; and

forming a first mask layer on the substrate, the first mask layer having an opening, the opening exposing the shielding material layer at the second side of the second patterned conductive layer; and

performing an anisotropic etching process on the shielding material layer exposed by the opening to expose the buffer layer.

12. The method of fabricating the non-volatile memory as recited in claim 11, wherein a material of the shielding material layer is different from a material of the spacer.

13. The method of fabricating the non-volatile memory as recited in claim 11, wherein a material of the shielding material layer comprises silicon oxide, silicon carbide, silicon carbonitride, silicon carbon oxide, silicon carbo-oxynitride, or a combination thereof.

14. The method of fabricating the non-volatile memory as recited in claim 11, wherein a material of the shielding material comprises silicon oxide using tetraethyl orthosilicate as a reactive gas.

15. The method of fabricating the non-volatile memory as recited in claim 10, wherein a material of the buffer material layer comprises silicon oxide.

16. The method of fabricating the non-volatile memory as recited in claim 10, wherein a method of forming the buffer material layer comprises performing a thermal oxidization process.

17. The method of fabricating the non-volatile memory as recited in claim 7, wherein a method of forming the recess on the first sidewall of the first patterned conductive layer comprises performing an isotropic etching process.

18. The method of fabricating the non-volatile memory as recited in claim 7, before forming the drain region, the method further comprising:

removing the tunneling dielectric layer not covered by the first patterned conductive layer and exposing a surface of the substrate, wherein the spacer, the second patterned conductive layer, the patterned inter-gate dielectric layer, the first patterned conductive layer, and the tunneling dielectric layer together constituting a first gate stack;

forming a first dielectric layer on the substrate, the first dielectric layer covering the spacer, the second patterned conductive layer, and the source region;

forming a second dielectric layer on the substrate between the drain region and the first gate stack; and

forming an erasing gate above the source region and forming a selecting gate on the second dielectric layer.

19. The method of fabricating the non-volatile memory as recited in claim 18, wherein the first gate stack further comprises a cap layer located on the second conductive layer.

20. The method of fabricating the non-volatile memory as recited in claim 18, further comprising forming a second gate stack on the substrate when the first gate stack is formed, the first and second gate stacks constituting a gate stack set, the method further comprising forming another drain region at a side of the second gate stack when the drain region is formed.