Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact

• US 20120261746A1
• Filed: 03/13/2012
• Published: 10/18/2012
• Est. Priority Date: 03/14/2011
• Status: Abandoned Application

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Blanchard, Richard A., Jun, Zeng
• Application Number:
  US13/418,615
• Publication Number:
  US 20120261746A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Methods and resulting device structures for power trench transistor fabrication, wherein a reachup pillar from the field plate trench is left in place to define the location of a self-aligned contact to the field plate.

Claims

1. A method of fabricating a semiconductor device, comprising the steps, in any order, of:

a) etching first and second trenches, simultaneously, into a semiconductor mass;

b) filling said first and second trenches, simultaneously, with a conductive material, while said semiconductor mass is overlaid by a sacrificial layer;

c) removing said sacrificial layer to expose pillars of said conductive material which rise above said semiconductor mass;

d) etching back said conductive material, over said first trench, to form a gate electrode therein;

e) forming a first-conductivity-type source region, and a second-conductivity-type body region therebelow, in said semiconductor mass; and

f) etching said conductive material over said second trench to form a cavity, introducing second-conductivity-type dopants to form body contact regions which are self-aligned to said second trench, and forming a metallic material in said cavity to provide a self-aligned contact to said body contact regions.

2. The method of claim 1, further comprising the additional step, after said step a), of forming a dielectric, at the bottom of said first trench, which is thicker than the dielectric at the bottom of said second trench.

3. The method of claim 1, wherein said semiconductor mass is silicon.

4. The method of claim 1, wherein said metallic material also makes electrical contact to said field plate.

5. The method of claim 1, wherein said conductive material is doped polysilicon.

6. The method of claim 1, wherein said first conductivity type is n-type, and said second conductivity type is p-type.

7. The method of claim 1, further comprising the additional step, prior to said step b), of growing a thin dielectric layer on sidewalls of said trenches.

8. The method of claim 1, wherein said gate electrode is entirely recessed below the surface of said semiconductor mass.

9. A method of fabricating a semiconductor device, comprising the steps, in any order, of:

a) etching first and second trenches, simultaneously, into a semiconductor mass;

b) filling said first and second trenches, simultaneously, with a solid material, while said semiconductor mass is overlaid by a sacrificial layer;

c) removing said sacrificial layer to expose pillars of said solid material which rise above said semiconductor mass;

d) etching back said solid material, over said first trench, and forming a gate electrode therein;

e) forming a first-conductivity-type source region and a second-conductivity-type body region in said semiconductor mass where said body region lies below said source region; and

f) etching back said conductive material over said second trench to form a cavity, introducing second-conductivity-type dopants into said cavity to thereby form body contact regions which are self-aligned to said second trench, and forming a metallic material in said cavity to connect to said body contact regions;

whereby the spacing between said body contact region and said gate electrode does not depend at all on lithographic misalignment.

10. The method of claim 9, wherein, in said step b), said solid material is never removed entirely from said first trench, and provides the material for said gate electrode.

11. The method of claim 9, further comprising the additional step, after said step a), of forming a dielectric, at the bottom of said first trench, which is thicker than the dielectric at the bottom of said second trench.

12. The method of claim 9, further comprising the additional step of forming a second-conductivity-type body region below said first-conductivity-type source region in said semiconductor mass.

13. The method of claim 10, further comprising the additional step of forming a second-conductivity-type body region below said first-conductivity-type source region in said semiconductor mass.

14. The method of claim 9, wherein said semiconductor mass is silicon.

15. The method of claim 9, wherein said first conductivity type is n-type, and said second conductivity type is p-type.

16. The method of claim 9, wherein said solid material is doped polysilicon.

17. The method of claim 9, further comprising the additional step, prior to said step b), of growing a thin dielectric layer on sidewalls of said trenches.

18. A semiconductor device, comprising:

source, body, drift, and drain regions, wherein said body region has a conductivity type opposite to those of said source and drain regions;

a conductive gate electrode in a first trench, which is electrostatically coupled, in at least some locations, to selectably invert a portion of said body region which adjoins said first trench;

a conductive field plate in a second trench;

wherein said first and second trenches having been formed by a single patterning step, and have no misalignment therebetween;

and a body contact region, having the same conductivity type as said body region, which is self-aligned to said second trench, independently of alignment variations;

whereby said body contact region also has a spacing, from said first trench, which is independent of any alignment variations.

19. A plurality of semiconductor devices according to claim 18.

20. The device of claim 19, wherein said semiconductor mass is silicon.

21-29. -29. (canceled)