MOSFET with Recessed channel FILM and Abrupt Junctions

• US 20120261754A1
• Filed: 04/14/2011
• Published: 10/18/2012
• Est. Priority Date: 04/14/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce, Khakifirooz, Ali, Kulkarni, Pranita
• Granted Patent: US 8,691,650 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

Claims

1. A method of making a metal oxide semiconductor field effect transistor (MOSFET), comprising:

providing a semiconductor on insulator layer (SOI layer);

forming a dummy gate on the SOI layer;

forming a plurality of first junctions by doping the SOI layer to form a doped SOI-source-drain;

forming an insulating layer over the SOI layer;

removing the dummy gate forming an exposed portion of the SOI layer;

etching the exposed portion of the SOI layer wherein the etching;

(i) forms a recess in the SOI layer;

(ii) leaves a remaining portion of the SOI layer below the recess; and

(iii) removes at least a portion of the first junctions;

filling the recess at least partially with a film to form a channel film and a plurality of second junctions between the channel film and the doped SOI-source-drain;

depositing a high dielectric constant material over the channel film; and

forming a metal gate stack in contact with the high dielectric constant material.

2. The method of claim 1, wherein the plurality of the first junctions are located where the doped SOI-source-drain meets the SOI layer.

3. The method of claim 1, wherein the MOSFET is a multigate device.

4. The method of claim 1, wherein the MOSFET has a gate width which is from about 5 nm to about 25 nm and ranges there between.

5. The method of claim 1, further comprising:

forming an off-set spacer prior to forming the first junctions.

6. The method of claim 1, wherein removing the dummy gate exposes at least a portion of the first junctions.

7. The method of claim 1, wherein etching is isotropic to create an undercut.

8. A semiconductor on insulator (SOI) substrate comprising:

a top surface of the substrate;

a doped SOI-source;

a doped SOI-drain;

a channel film between the doped SOI-source and the doped SOI-drain wherein the channel film has a channel top surface; and

a remaining SOI layer under the channel film.

9. The substrate of claim 8, wherein a channel film thickness is greater than a remaining SOI layer thickness.

10. The substrate of claim 8, wherein the substrate top surface is higher than the channel top surface thereby creating a step height from the channel film top surface to the substrate top surface.

11. The substrate of claim 10, wherein the step height is from about 1 nm to about 10 nm and ranges there between.

12. The substrate of claim 8, wherein the channel film abuts the doped SOI-source and the doped SOI-drain to form a channel-source junction and a channel-drain junction wherein the channel-source junction and the channel-drain junction are sharp junctions.

13. The substrate of claim 8, wherein the remaining SOI layer abuts the doped SOI-source and abuts the doped SOI-drain to form a remaining-source junction and a remaining-drain junction wherein the remaining-source junction and the remaining-drain junction are diffuse junctions.

14. The substrate of claim 12, wherein the sharp junctions have a dopant gradient from about 0.5 nm per decade to about to 3 nm per decade and ranges there between.

15. The substrate of claim 12, wherein the diffuse junctions have a dopant gradient from about 3 nm per decade to about 10 nm per decade and ranges there between.

16. A metal oxide semiconductor field effect transistor (MOSFET) comprising:

a doped SOI-source;

a doped SOI-drain;

an insulator layer above the doped SOI-source and doped SOI-drain;

a channel film between the doped SOI-source and the doped SOI-drain wherein the channel film has a top surface;

a remaining SOI layer under the channel film;

an opening in the insulator wherein the opening is above at least a portion of the channel film;

a high dielectric constant material in contact with at least a portion of the channel film; and

a metal gate in contact with the high dielectric constant material.

17. The MOSFET of claim 16, further comprising:

a gate width which is from about 5 nm to about 25 nm and ranges there between.

18. The MOSFET of claim 16, wherein:

the channel film has a plurality of sidewalls;

the high dielectric constant material has a plurality of outer surfaces; and

at least one of the channel film sidewalls aligns vertically with one of the dielectric constant material outer surfaces.

19. The MOSFET of claim 16, wherein:

the channel film has a channel film width; and

the channel film width is from about 5 nm to about 50 nm and ranges there between.

20. The MOSFET of claim 16, further comprising:

a raised source above the doped SOI-source; and

a raised drain above the doped SOI-drain.