METHOD OF FABRICATING A GATE DIELECTRIC LAYER

• US 20120261758A1
• Filed: 04/14/2011
• Published: 10/18/2012
• Est. Priority Date: 04/14/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Wei-Yang, YU, Xiong-Fei, LEE, Da-Yuan, HSU, Kuang-Yuan
• Granted Patent: US 8,952,458 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate having a first active region; a first gate structure over the first active region, wherein the first gate structure comprises a first interfacial layer having a convex top surface; a first high-k dielectric over the first interfacial layer; and a first gate electrode over the first high-k dielectric.

Claims

1. A semiconductor device comprising:

a substrate having a first active region;

a first gate structure over the first active region, wherein the first gate structure comprises

a first interfacial layer having a convex top surface;

a first high-k dielectric over the first interfacial layer; and

a first gate electrode over the first high-k dielectric.

2. The semiconductor device of claim 1, wherein the first interfacial layer comprises fluorine-doped silicon oxide or fluorine-doped silicon oxynitride.

3. The semiconductor device of claim 2, wherein a fluorine concentration of the first interfacial layer is in the range of about 2% to 8% in terms of atomic percent.

4. The semiconductor device of claim 1, wherein the convex top surface comprises a highest point skewed toward an edge of the convex top surface.

5. The semiconductor device of claim 1, wherein a ratio of a minimum thickness of the first interfacial layer to a maximum thickness of the first interfacial layer is from 0.5 to 0.7.

6. The semiconductor device of claim 1, wherein the first high-k dielectric comprises a fluorine-doped high-k dielectric.

7. The semiconductor device of claim 6, wherein a fluorine concentration of the fluorine-doped high-k dielectric is in the range of about 2% to 8% in terms of atomic percent.

8. The semiconductor device of claim 6, wherein the fluorine-doped high-k dielectric comprises fluorine-doped hafnium oxide.

9. The semiconductor device of claim 1 further comprising a second gate structure over a second active region, wherein the second gate structure comprises

a second interfacial layer having a concave top surface;

a second high-k dielectric over the second interfacial layer; and

a second gate electrode over the second high-k dielectric.

10. The semiconductor device of claim 9, wherein the second interfacial layer comprises silicon oxide or silicon oxynitride.

11. The semiconductor device of claim 9, wherein the concave top surface comprises a lowest point skewed toward an edge of the concave top surface.

12. The semiconductor device of claim 9, wherein a ratio of a minimum thickness of the second interfacial layer to a maximum thickness of the second interfacial layer is from 0.6 to 0.8.

13. The semiconductor device of claim 9, wherein a maximum thickness of the second interfacial layer is less than a maximum thickness of the first interfacial layer.

14. The semiconductor device of claim 13, wherein a ratio of a maximum thickness of the second interfacial layer to a maximum thickness of the first interfacial layer is from 0.3 to 0.9.

15. The semiconductor device of claim 9, wherein the first gate structure is a portion of an input/output (I/O) device and the second gate structure is a portion of a core device.

16. A method for fabricating a gate dielectric layer, comprising:

forming an interfacial layer over a substrate;

forming a high-k dielectric on the interfacial layer; and

performing a fluorine-containing plasma treatment on the high-k dielectric and interfacial layer.

17. The method of claim 16, wherein the step of performing a fluorine-containing plasma treatment is performed using a chemical selected from NF₃, CF₄, and SF₆ as a fluorine source gas.

18. The method of claim 16, wherein the step of performing a fluorine-containing plasma treatment is performed under a pressure of about 50 mTorr to 100 mTorr.

19. The method of claim 16, wherein the step of performing a fluorine-containing plasma treatment is performed at a temperature of about 100°

C. to 350°

C.

20. The method of claim 16, wherein the step of performing a fluorine-containing plasma treatment is performed under a source power of about 500 to 3000 W.