Wide and Deep Oxide Trench in A Semiconductor Substrate with Interspersed Vertical Oxide Ribs

• US 20120261791A1
• Filed: 06/29/2012
• Published: 10/18/2012
• Est. Priority Date: 12/15/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Xiaobin, Bhalla, Anup, Lee, Yeeherg
• Granted Patent: US 8,642,429 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76227 the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

Claims

1. A method of forming a large deep oxide trench in a semiconductor substrate comprising:

a) forming, in the semiconductor substrate, a plurality of interim trenches separated by a corresponding number of remaining semiconductor mesas between the interim trenches; and

b) oxidizing the remaining semiconductor mesas until they are substantially converted to oxide.

2. The method of claim 1 further comprising:

c) filling up any remaining spaces of the interim trenches with insulating material.

3. The method of claim 2 wherein filling up any remaining spaces further comprises filling up any remaining spaces of the interim trenches with oxide.

4. The method of claim 1 wherein oxidizing the remaining semiconductor mesas is via thermal oxidation.

5. The method of claim 1 wherein oxidizing the remaining semiconductor mesas further comprises oxidizing the semiconductor mesas until all the semiconductor material in the mesas is converted to oxide.

6. A wide and deep oxide trench in a semiconductor substrate comprising vertical oxide ribs, being made of thermal oxide, interspersed throughout the wide and deep oxide trench.

7. The wide and deep oxide trench of claim 6 wherein any remaining spaces between the vertical oxide ribs are filled with an insulating material.

8. The wide and deep oxide trench of claim 6 wherein any remaining spaces between the vertical oxide ribs are filled with deposited oxide.

9. The wide and deep oxide trench of claim 6 wherein the vertical oxide ribs contain a small notch at their bottoms.