POWER SUPPLY WTH DIGITAL FEEDBACK SIGNALING

• US 20120262956A1
• Filed: 04/18/2011
• Published: 10/18/2012
• Est. Priority Date: 04/18/2011
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: DeHaven, Maxwell Scott
• Granted Patent: US 8,908,394 B2
• Time in Patent Office: Days
• US Class Current: 363/21.09
• CPC Class Codes: H02M 3/33515 with digital control

Abstract

Apparatus and methods are provided for use with power supplies. A controller regulates power supply output by way of feedback signaling. Current pulses generated by an electrical load are detected in the feedback signaling and are processed to derive a sequence of digital bits. The digital, bits are subjected to validity testing and decoded as digital data. Operations of the power supply are adjusted and requests for information are answered in accordance with the digital data.

Claims

1. Electronic circuitry configured to:

apply a moving average filter to an electrical feedback signal to derive a filtered signal;

compare the filtered signal to a pair of threshold values to derive a digital bit stream;

provide the digital bit stream to an asynchronous decoder state machine (ADSM) including a register and a bit counter, the ADSM loading the digital bit stream into the register and incrementing the bit counter in accordance with validity testing states;

parse the contents of the register using the bit counter to derive digital data; and

adjust an operating parameter of an electrical power supply in accordance with the digital data.

2. The electronic circuitry according to claim 1, the ADSM configured such that the validity testing states include:

detecting an idle period spanning four consecutive bit-times within the digital bit stream;

detecting a valid sequence of start bits within the digital bit stream; and

detecting valid rising edges and valid falling edges and valid bit-times within the digital bit stream.

3. The electronic circuitry according to claim 1, the ADSM further configured to reset the register and the bit counter to respective default values in response to detecting an invalid event by way of the validity testing states.

4. The electronic circuitry according to claim 1, the moving average filter operating by way of averaging a most recent eight consecutive samplings of the electrical feedback signal.

5. The electronic circuitry according to claim 1 further configured to sense, the electrical feedback signal by way of a secondary winding of a transformer electrically coupled to the electronic circuitry.

6. The electronic circuitry according to claim 1, the electrical feedback signal corresponding to pulses of electrical current through a load.

7. The electronic circuitry according to claim 1, further configured such that the digital bit stream is characterized by respective rising edges and falling edges.

8. The electronic circuitry according to claim 1, the operating parameter of the power supply including at least a course voltage calibration, or a fine voltage calibration.

9. The electronic circuitry according to claim 1, further configured to communicate information regarding a characteristic of the power supply in response to the digital data.

10. The electronic circuitry according, to, claim 1, at least the ADSM provided by way of an application-specific integrated circuit.

11. A controller configured to:

regulate an output of electrical energy from a power supply by way of feedback signaling, the feedback signaling provided by way of a secondary winding of a transformer of the power supply;

sense pulse signals from a load by way of the feedback signaling;

process the pulse signals to derive digital data; and

adjust respective operating parameters of the power supply in accordance with the digital data.

12. The controller according to claim 11, further configured to:

filter the pulse signals by way of a moving average filter to derive a filtered signal; and

compare the filtered signal to a pair of threshold values to derive a digital bit stream characterized by respective rising edges and falling edges.

13. The controller according to claim 12, further configured to:

detect an idle period within the digital bit stream;

detect valid rising edges and falling edges and bit-times within the digital bit stream;

detect a valid start bit-sequence within the digital bit stream;

load a bit-shift register using the digital bit stream; and

increment a counter in accordance with the loading of the bit-shift register.

14. The controller according to claim 13, further configured to parse the contents of the bit-shift register by way of the counter to derive the digital data.

15. The controller according to claim 13, further configured to reset the bit-shift register and the counter to respective initial values in response to detecting an invalid event in the digital bit stream.

16. A storage media including a program code, the program code configured to cause one or more processors to:

encode a digital message to be sent to a power supply;

modulate an electrical current to derive a sequence of pulses in accordance with the digital message;

receive a digital reply from the power supply; and

control an apparatus receiving electrical energy from the power supply in accordance with the digital reply.

17. An asynchronous decoder state machine configured to:

detect of a predefined idle period within a digital bit stream;

detect valid rising edges and falling edges and bit-times within the digital bit stream;

detect a valid sequence of start bits within the digital bit stream;

load the digital bit stream into a register and increment a bit counter in accordance with the loading; and

reset the register and the bit counter to respective start values in response to detecting an invalid event within the digital bit stream.