METHOD OF FABRICATING SEMICONDUCTOR COMPONENT

• US 20120264300A1
• Filed: 04/13/2011
• Published: 10/18/2012
• Est. Priority Date: 04/13/2011
• Status: Abandoned Application

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Liao, Chien-Mao, Chen, Yi-Nan, Liu, Hsien-Wen
• Application Number:
  US13/086,366
• Publication Number:
  US 20120264300A1
• Time in Patent Office: Days
• US Class Current: 438/692
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

A method of fabricating the semiconductor component including following steps is provided. A substrate is provided, wherein an opening is already formed in the substrate. A material layer is formed on the substrate, wherein the material layer fills up the opening, and the material layer outside and above the opening has a recess therein. A sacrifice layer is formed on a surface of the recess. A chemical mechanical polishing (CMP) process is performed to remove the sacrifice layer and the material layer outside the opening, wherein a polishing rate of the CMP process on the material layer is greater than that of the CMP process on the sacrifice layer.

Claims

1. A method of fabricating a semiconductor component, comprising:

providing a substrate, wherein an opening is already formed in the substrate;

forming a material layer on the substrate, wherein the material layer fills up the opening, and the material layer outside and above the opening has a recess therein;

forming a sacrifice layer on a surface of the recess; and

performing a chemical mechanical polishing (CMP) process to remove the sacrifice layer and the material layer outside the opening, wherein a polishing rate of the CMP process on the material layer is greater than a polishing rate of the CMP process on the sacrifice layer.

2. The method of fabricating the semiconductor component according to claim 1, wherein a depth of the opening is between 70 μ

m and 150 μ

m.

3. The method of fabricating the semiconductor component according to claim 1, wherein a width of the opening is between 10 μ

m and 40 μ

m.

4. The method of fabricating the semiconductor component according to claim 1, wherein an aspect ratio of the opening is between 1.8 and 15.

5. The method of fabricating the semiconductor component according to claim 1, wherein a step height of the recess is between 2 μ

m and 4 μ

m.

6. The method of fabricating the semiconductor component according to claim 1, wherein a material of the material layer comprises a metal material.

7. The method of fabricating the semiconductor component according to claim 1, wherein a method of forming the sacrifice layer comprises:

forming a sacrifice material layer on the material layer; and

removing the sacrifice material layer outside the recess.

8. The method of fabricating the semiconductor component according to claim 7, wherein a method of removing the sacrifice material layer outside the recess comprises a CMP method.

9. The method of fabricating the semiconductor component according to claim 1, wherein a material of the sacrifice layer comprises a dielectric material.

10. The method of fabricating the semiconductor component according to claim 1, wherein the semiconductor component comprises a through-silicon via (TSV) structure.