DATA PROCESSING DEVICE AND DATA PROCESSING METHOD THEREOF

• US 20120265964A1
• Filed: 02/03/2012
• Published: 10/18/2012
• Est. Priority Date: 02/22/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Haraguchi, Masaru, MURATA, Kan, Noda, Hideyuki
• Granted Patent: US 9,558,151 B2
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 2207/3812 Devices capable of handling different types of numbers
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic operation on data stored in a corresponding one of the SRAMs. The second PEs each perform an arithmetic operation on data stored in corresponding ones of the SRAMs. Therefore, the SRAMs can be shared so as to efficiently perform the arithmetic process on variable-length data and the arithmetic process on fixed-length data.

Claims

1. A data processing device comprising:

a plurality of first processors of SIMD arithmetic type;

a plurality of memories provided respectively for the first processors; and

a plurality of second processors;

wherein the first processors each perform an arithmetic operation on data stored in a corresponding one of the memories; and

wherein the second processors each perform an arithmetic operation on data stored in corresponding ones of the memories.

2. The data processing device according to claim 1,

wherein the first processors perform an arithmetic operation on variable-bit length data, and

wherein the second processors perform an arithmetic operation on fixed-bit length data.

3. The data processing device according to claim 1, further comprising:

an orthogonal transducer that orthogonally transforms data,

wherein the orthogonal transducer receives data from the outside, orthogonally transforms the received data, stores the transformed data in the memories as the data for the first processors, and stores the received data in the memories directly as the data for the second processors.

4. The data processing device according to claim 3, wherein the orthogonal transducer orthogonally transforms the results of computations performed by the first processors, which are stored in the memories, and outputs the transformed computation results to the outside, and outputs the results of computations performed by the second processors, which are stored in the memories, directly to the outside.

5. The data processing device according to claim 1, further comprising:

a data mover that is disposed between the memories and the first and second processors to move and supply data stored in the memories to a first processor other than the corresponding first processors.

6. The data processing device according to claim 1, further comprising:

an instruction memory that stores a microcode program; and

a controller that interprets the microcode program stored in the instruction memory and selectively causes the first processors and the second processors to perform an arithmetic process.

7. The data processing device according to claim 1, wherein the second processors each include a floating-point arithmetic unit and perform an arithmetic process upon receipt of data from some number of the memories, the number of which corresponds to the data length of the floating-point arithmetic unit.

8. The data processing device according to claim 1, wherein the second processors each include a product-sum arithmetic unit and perform an arithmetic process upon receipt of data from some number of the memories, the number of which corresponds to the data length of the product-sum arithmetic unit.

9. A data processing method for causing a data processing device to perform signal processing for a millimeter-wave radar,

wherein the data processing device includes:

a plurality of first processors of SIMD arithmetic type;

a plurality of memories provided respectively for the first processors; and

a plurality of second processors provided for plural ones of the memories,

the data processing method comprising the steps of;

causing the first processors to compute data stored in the memories to perform a gain adjustment process and a clipping process on data obtained when information acquired by the millimeter-wave radar is converted to digital equivalent;

causing the first processors to perform a thinning process and a filtering process on the data derived from the clipping process;

causing the first processors or the second processors to convert the data derived from the filtering process to a floating-point value and store the floating-point value in the memories; and

causing the second processors to perform a fast Fourier transform with the floating-point value stored in the memories.