SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20120267623A1
• Filed: 04/13/2012
• Published: 10/25/2012
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ISOBE, Atsuo, SASAKI, Toshinari, SASAGAWA, Shinya, ISHIZUKA, Akihiro
• Granted Patent: US 8,916,868 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

Claims

1. A semiconductor device comprising:

a trench provided in an insulating layer, wherein the trench includes a lower end corner portion and an upper end corner portion having a curved shape;

an oxide semiconductor film in contact with a bottom surface, an inner wall surface, the lower end corner portion, and the upper end corner portion of the trench;

a source electrode layer and a drain electrode layer over the oxide semiconductor film;

a gate insulating layer over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and

a gate electrode layer over the gate insulating layer,

wherein the upper end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor film at least over the upper end corner portion.

3. The semiconductor device according to claim 1, wherein a surface of the insulating layer in the upper end corner portion has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

4. The semiconductor device according to claim 1, wherein a surface of the insulating layer in the lower end corner portion has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

5. The semiconductor device according to claim 1, wherein a surface of the insulating layer in contact with the oxide semiconductor film has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

6. The semiconductor device according to claim 1, wherein the trench is filled with the gate electrode layer.

7. A memory device comprising the semiconductor device according to claim 1.

8. A semiconductor device comprising:

a trench provided in an insulating layer, wherein the trench includes a lower end corner portion having a curved shape and an upper end corner portion having a curved shape;

an oxide semiconductor film in contact with a bottom surface, an inner wall surface, the lower end corner portion, and the upper end corner portion of the trench;

a source electrode layer and a drain electrode layer over the oxide semiconductor film;

a gate insulating layer over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and

a gate electrode layer over the gate insulating layer,

wherein the upper end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm,

wherein the lower end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

9. The semiconductor device according to claim 8, wherein the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor film at least over the lower end corner portion and the upper end corner portion

10. The semiconductor device according to claim 8, wherein a surface of the insulating layer in the upper end corner portion has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

11. The semiconductor device according to claim 8, wherein a surface of the insulating layer in the lower end corner portion has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

12. The semiconductor device according to claim 8, wherein a surface of the insulating layer in contact with the oxide semiconductor film has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm.

13. The semiconductor device according to claim 8, wherein the trench is filled with the gate electrode layer.

14. A memory device comprising the semiconductor device according to claim 8.

15. A semiconductor device comprising:

a first transistor comprising;

a channel formation region including a semiconductor material; and

a first gate electrode overlapping with the channel formation region,

an insulating layer covering the first transistor, wherein part of the first gate electrode is exposed without being covered with the insulating layer,

a second transistor comprising;

a trench provided in the insulating layer, wherein the trench includes an upper end corner portion having a curved shape;

an oxide semiconductor film in contact with a bottom surface, a lower end corner portion, the upper end corner portion and an inner wall surface of the trench;

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor film;

a gate insulating layer over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and

a second gate electrode layer over the gate insulating layer,

wherein the upper end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and

wherein one of the source electrode layer and the drain electrode layer of the second transistor is in direct contact with the part of the first gate electrode.

16. The semiconductor device according to claim 15, further comprising a capacitor, wherein the capacitor comprises one of the source electrode layer and the drain electrode layer, the gate insulating layer, and an electrode provided over the gate insulating layer.

17. The semiconductor device according to claim 15, wherein the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor film at least over the lower end corner portion.

18. The semiconductor device according to claim 15, wherein the trench is filled with the second gate electrode layer.

19. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating layer provided with a trench including a lower end corner portion and an upper end corner portion;

processing the upper end corner portion into a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm;

forming an oxide semiconductor film in contact with a bottom surface, an inner wall surface, the lower end corner portion, and the upper end corner portion of the trench;

forming a gate insulating layer over the oxide semiconductor film; and

forming a gate electrode layer over the gate insulating layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein the oxide semiconductor film has a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor film at least over the upper end corner portion

21. The method for manufacturing a semiconductor device according to claim 19, wherein the upper end corner portion of the insulating layer is processed by plasma treatment into the curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

22. The method for manufacturing a semiconductor device according to claim 19, wherein the lower end corner portion is processed into a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

23. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating layer provided with a trench including a lower end corner portion and an upper end corner portion;

processing the upper end corner portion into a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm;

forming an oxide semiconductor film in contact with a bottom surface, an inner wall surface, the lower end corner portion, and the upper end corner portion of the trench;

forming a gate insulating layer over the oxide semiconductor film; and

forming a gate electrode layer over the gate insulating layer,

wherein the oxide semiconductor film is formed while heating the insulating layer so as to include a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

24. The method for manufacturing a semiconductor device according to claim 23, wherein the upper end corner portion of the insulating layer is processed by plasma treatment into the curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

25. The method for manufacturing a semiconductor device according to claim 23, wherein the lower end corner portion is processed into a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

26. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating layer provided with a trench including a lower end corner portion and an upper end corner portion;

processing the upper end corner portion into a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm;

forming an amorphous oxide semiconductor film in contact with a bottom surface, an inner wall surface, the lower end corner portion, and the upper end corner portion of the trench;

performing heat treatment on the amorphous oxide semiconductor film to form an oxide semiconductor film including a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion;

forming a gate insulating layer over the oxide semiconductor film; and

forming a gate electrode layer over the gate insulating layer.

27. The method for manufacturing a semiconductor device according to claim 26, wherein the upper end corner portion of the insulating layer is processed by plasma treatment into the curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.

28. The method for manufacturing a semiconductor device according to claim 26, wherein the lower end corner portion is processed into a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm.