TRANSISTOR ARRANGEMENT WITH A MOSFET

• US 20120267704A1
• Filed: 04/22/2011
• Published: 10/25/2012
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Siemieniec, Ralf, Schulze, Hans-Joachim
• Granted Patent: US 8,587,059 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A semiconductor arrangement includes a MOSFET having a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a source electrode contacting the source region and the body region. The semiconductor arrangement further includes a normally-off JFET having a channel region of the first conductivity type that is coupled between the source electrode and the drift region and extends adjacent the body region so that a p-n junction is formed between the body region and the channel region.

Claims

1. A semiconductor arrangement, comprising:

a MOSFET comprising a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a source electrode contacting the source region and the body region; and

a normally-off JFET comprising a channel region of the first conductivity type that is coupled between the source electrode and the drift region and extends adjacent the body region so that a p-n junction is formed between the body region and the channel region.

2. The semiconductor arrangement of claim 1, wherein the body region has a basic doping with a first doping concentration and comprises a channel control region of the second conductivity type, wherein the junction control region has a higher doping concentration than the basic doping, is electrically connected to the source electrode and adjoins the channel region.

3. The semiconductor arrangement of claim 2, wherein the semiconductor body comprises a first surface, and wherein the channel control region is arranged distant to the first surface.

4. The semiconductor arrangement of claim 3, wherein a distance between the first surface and the channel control region is between 0.1 μ

m and 3 μ

m.

5. The semiconductor arrangement of claim 1, further comprising a semiconductor body in which the source region and the drain region are arranged distant to each other in a vertical direction of the semiconductor body.

6. The semiconductor arrangement of claim 5, wherein the channel region extends in a vertical direction of the semiconductor body along the body region.

7. The semiconductor arrangement of claim 1, further comprising a contact region of the first conductivity type arranged between the channel region and the source electrode and having a higher doping concentration than the channel region.

8. The semiconductor arrangement of claim 1, wherein a doping concentration of the channel region corresponds to a doping concentration of the drift region.

9. The semiconductor arrangement of claim 1, wherein the channel region adjoins the drift region.

10. The semiconductor arrangement of claim 1, wherein a doping concentration of the channel region corresponds to a doping concentration of the drift region.

11. The semiconductor arrangement of claim 1, wherein the doping concentration of the channel region is between 10¹³ cm⁻

3 and 2·

10¹⁷ cm<sup>−

3</sup>, or between 10¹³ cm<sup>−

3</sup> and 10¹⁵ cm<sup>−

3</sup>.

12. The semiconductor arrangement of claim 1, wherein the JFET has a current flow direction and the channel has a width in a direction perpendicular to the current flow direction, the width being between 0.1 and 0.8 μ

m.

13. The semiconductor arrangement of claim 1, wherein the JFET has a current flow direction and the body region surrounds the channel region in a direction perpendicular to the current flow direction.

14. The semiconductor arrangement of claim 1, further comprising an insulation layer adjoining the channel region at a side opposite the body region.

15. The semiconductor arrangement of claim 1, wherein:

the JFET has a current flow direction and the channel has a width in a direction perpendicular to the current flow direction;

an intrinsic depletion region is disposed at the p-n junction between the body region and the channel region when the MOSFET is in an unbiased state;

a width of the intrinsic depletion region is dependent on a doping concentration of the channel region; and

the doping concentration of the channel region is such that the width of the depletion region is larger than the width of the channel.

16. A MOSFET, comprising:

a semiconductor body with a source region, a drift region and a drain region of a first conductivity type, and a body region of a second conductivity type arranged between the source region and the drift region;

a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric;

a source electrode contacting the source region and the body region; and

a channel region of the first conductivity type extending from the source electrode to the drift region adjacent to the body region, so that a p-n junction is formed between the body region and the channel region, wherein a doping concentration of the body region and a width of the channel region is such that an intrinsic depletion zone pinches off the channel region when the MOSFET is in an unbiased state.

17. The MOSFET of claim 16, wherein the body region has a basic doping with a first doping concentration and comprises a junction control region of the second conductivity type, wherein the junction control region has a higher doping concentration than the basic doping, is electrically connected to the source electrode and adjoins the channel region.

18. The MOSFET of claim 16, further comprising a semiconductor body in which the source region and the drain region are arranged distant to each other in a vertical direction of the semiconductor body.

19. The MOSFET of claim 16, wherein the channel region extends in a vertical direction of the semiconductor body along the body region.

20. The MOSFET of claim 16, further comprising a contact region of the first conductivity type arranged between the channel region and the source electrode and having a higher doping concentration than the channel region.

21. The MOSFET of claim 16, wherein a doping concentration of the channel region corresponds to a doping concentration of the drift region.

22. The MOSFET of claim 16, wherein the channel region adjoins the drift region.

23. The MOSFET of claim 16, wherein a doping concentration of the channel region corresponds to a doping concentration of the drift region.

24. The MOSFET of claim 16, wherein the doping concentration of the channel region is between 10¹³ cm⁻

3 and 2·

10¹⁷ cm<sup>−

3</sup>, or between 10¹³ cm<sup>−

3</sup> and 10¹⁵ cm<sup>−

3</sup>.

25. The MOSFET of claim 16, wherein the JFET has a current flow direction and wherein the channel has a width in a direction perpendicular to the current flow direction, wherein this width is between 0.1 μ

m and 0.8 μ

m.

26. The MOSFET of claim 16, wherein the body region surrounds the channel region in a direction perpendicular to a current flow direction.

27. The MOSFET of claim 16, further comprising an insulation layer adjoining the channel region at a side opposite the body region.