SCAN SIGNAL LINE DRIVER CIRCUIT, DISPLAY DEVICE, AND METHOD OF DRIVING SCAN SIGNAL LINES

• US 20120268441A1
• Filed: 06/05/2012
• Published: 10/25/2012
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Shenzhen Torey Microelectronic Technology Co., Ltd.
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: WATANABE, Takuya
• Granted Patent: US 8,654,115 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/045 Protection against panel overheating
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3666 with the matrix divided into sections
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A gate driver includes: a scan signal output circuit for performing alternately scanning whereby either odd-numbered scan signal lines or even-numbered scan signal lines are sequentially driven and scanning whereby the remaining scan signal lines are sequentially driven; a rise counter circuit for sensing the rise count for a clock signal in a HIGH level period of an externally supplied start signal; a scan sequence setup circuit for setting up a scan sequence to be followed by the scan signal output circuit according to the rise count; and a start signal generating circuit for generating a start signal to be supplied to a next scan signal line driver circuit. Hence, the resultant scan signal line driver circuit and method thereof is capable of producing high quality images at low cost while restricting power consumption and heat generation by a data signal line driver circuit.

Claims

1. A scan signal line driver circuit driving scan signal lines of a display screen according to an externally supplied start signal and an externally supplied clock signal, said scan signal line driver circuit comprising:

a clock pulse counter circuit for sensing, as a first count, either a rise count or a fall count for the clock signal in a HIGH level period of the externally supplied start signal; and

a drive mode selecting circuit for selecting, according to the first count, either a first drive mode in which the scan signal lines are driven in a predetermined sequence or a second drive mode in which the scan signal lines are all simultaneously driven.

2. The scan signal line driver circuit as set forth in claim 1, wherein:

said scan signal line driver circuit is cascaded to another scan signal line driver circuit and further comprises a start signal generating circuit for generating a start signal to be supplied to a next scan signal line driver circuit according to the first count; and

when the drive mode selecting circuit selects the second drive mode, a second count which is either the rise count or the fall count for the clock signal in a HIGH level period of the start signal generated by the start signal generating circuit is a count according to which the drive mode selecting circuit selects the second drive mode.

3. The scan signal line driver circuit as set forth in claim 1, further comprising a power-on reset circuit for sensing a startup of a power supply and generating a power-on reset signal,

wherein:

the clock pulse counter circuit includes a counter for counting either the rise count or the fall count for the clock signal; and

when the power supply is turned on, the counter is reset in response to the power-on reset signal.

4. A display device, comprising the scan signal line driver circuit as set forth in claim 1.

5. A method of driving a display device including a scan signal line driver circuit, said method comprising:

the rise counting step of sensing, as a first count, either a rise count or a fall count for a clock signal supplied to the scan signal line driver circuit in a HIGH level period of a start signal supplied to the scan signal line driver circuit; and

the drive mode selecting step of selecting, according to the first count, either a first drive mode in which scan signal lines of a display screen are driven in a predetermined sequence or a second drive mode in which the scan signal lines are all simultaneously driven.

6. The method as set forth in claim 5, wherein:

the scan signal line driver circuit is cascaded to another scan signal line driver circuit;

said method further comprises the start signal generating step of generating a start signal to be supplied to a next scan signal line driver circuit according to the first count; and

when the drive mode selecting step selects the second drive mode, a second count which is either the rise count or the fall count for the clock signal in a HIGH level period of the start signal generated in the start signal generating step is a count according to which the drive mode selecting step selects the second drive mode.