SEMICONDUCTOR DEVICE

• US 20120268979A1
• Filed: 04/18/2012
• Published: 10/25/2012
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sekine, Yusuke
• Granted Patent: US 8,797,788 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from the stored data holding portion is prevented. As the transistor whose off-state current is small provided for preventing leakage of electric charge from the stored data holding portion, a transistor including an oxide semiconductor film is preferably used. Such a configuration can also be applied to a shift register, whereby a shift register with low power consumption can be obtained.

Claims

1. A semiconductor device comprising a first memory comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor electrically connected to each other in series in order; and

a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor electrically connected to each other in series in order,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the fifth transistor are electrically connected to a high power supply potential line,

wherein one of a source and a drain of the fourth transistor and one of a source and a drain of the eighth transistor are electrically connected to a low power supply potential line,

wherein a gate of the second transistor, a gate of the third transistor, a gate of the sixth transistor, and a gate of the seventh transistor are electrically connected to a first terminal,

wherein a gate of the fifth transistor and a gate of the eighth transistor are electrically connected to a second terminal,

wherein the second terminal is electrically connected between the second transistor and the third transistor,

wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to a third terminal,

wherein the third terminal is electrically connected between the sixth transistor and the seventh transistor,

wherein each of the first transistor and the fifth transistor is a p-channel transistor,

wherein each of the second transistor, the third transistor, the sixth transistor, and the seventh transistor is a transistor comprising an oxide semiconductor layer, and

wherein each of the fourth transistor and the eighth transistor is an n-channel transistor.

2. The semiconductor device according to claim 1 further comprising:

a second memory having a structure similar to that of the first memory;

a ninth transistor; and

a tenth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to the third terminal of the first memory,

wherein one of a source and a drain of the tenth transistor is electrically connected to the second terminal of the first memory, and

wherein the other of the source and the drain of the tenth transistor is electrically connected to the third terminal of the second memory.

3. The semiconductor device according to claim 2,

wherein a gate of the ninth transistor is electrically connected to a line to which a clock signal is input,

wherein a gate of the tenth transistor is electrically connected to a line to which an inversion signal of the clock signal is input, and

wherein the other of the source and the drain of the ninth transistor is electrically connected to a data input signal line.

4. A semiconductor device comprising a first memory comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor electrically connected to each other in series in order; and

a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor electrically connected to each other in series in order,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the fifth transistor are electrically connected to a high power supply potential line,

wherein one of a source and a drain of the fourth transistor and one of a source and a drain of the eighth transistor are electrically connected to a low power supply potential line,

wherein a gate of the first transistor, a gate of the fourth transistor, a gate of the fifth transistor, and a gate of the eighth transistor are electrically connected to a first terminal,

wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a second terminal,

wherein the second terminal is electrically connected between the second transistor and the third transistor,

wherein a gate of the second transistor and a gate of the third transistor are electrically connected to a third terminal,

wherein the third terminal is electrically connected between the sixth transistor and the seventh transistor,

wherein each of the first transistor, the fourth transistor, the fifth transistor, and the eighth transistor is a transistor comprising an oxide semiconductor layer,

wherein each of the second transistor and the sixth transistor is a p-channel transistor, and

wherein each of the third transistor and the seventh transistor is an n-channel transistor.

5. The semiconductor device according to claim 4 further comprising:

a second memory having a structure similar to that of the first memory;

a ninth transistor; and

a tenth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to the third terminal of the first memory, and

wherein one of a source and a drain of the tenth transistor is electrically connected to the second terminal of the first memory and the third terminal of the second memory.

6. The semiconductor device according to claim 5,

wherein a gate of the ninth transistor is electrically connected to a line to which a clock signal is input,

wherein a gate of the tenth transistor is electrically connected to a line to which an inversion signal of the clock signal is input, and

wherein the other of the source and the drain of the ninth transistor is electrically connected to a data input signal line.

7. A semiconductor device comprising a first memory comprising:

a first transistor, a second transistor, and a third transistor electrically connected to each other in series in order; and

a fourth transistor, a fifth transistor, and a sixth transistor electrically connected to each other in series in order,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor are electrically connected to a high power supply potential line,

wherein one of the source and the drain of the third transistor and one of the source and the drain of the sixth transistor are electrically connected to a low power supply potential line,

wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a third terminal,

wherein the third terminal is electrically connected between the fifth transistor and the sixth transistor,

wherein a gate of the fourth transistor and a gate of the sixth transistor are electrically connected to a second terminal,

wherein the second terminal is electrically connected between the second transistor and the third transistor,

wherein a gate of the second transistor and a gate of the fifth transistor are electrically connected to a first terminal,

wherein each of the first transistor and the fourth transistor is a p-channel transistor, and

wherein each of the second transistor, the third transistor, the fifth transistor, and the sixth transistor is a transistor comprising an oxide semiconductor layer.

8. The semiconductor device according to claim 7 further comprising:

a second memory having a structure similar to that of the first memory;

a seventh transistor; and

a eighth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the third terminal of the first memory, and

wherein one of a source and a drain of the eighth transistor is electrically connected to the second terminal of the first memory and the third terminal of the second memory.

9. The semiconductor device according to claim 8,

wherein a gate of the seventh transistor is electrically connected to a line to which a clock signal is input,

wherein a gate of the eighth transistor is electrically connected to a line to which an inversion signal of the clock signal is input, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to a data input signal line.

10. A semiconductor device comprising a first memory comprising:

a first transistor, a second transistor, and a third transistor electrically connected to each other in series in order; and

a fourth transistor, a fifth transistor, and a sixth transistor electrically connected to each other in series in order,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor are electrically connected to a high power supply potential line,

wherein one of the source and the drain of the third transistor and one of the source and the drain of the sixth transistor are electrically connected to a low power supply potential line,

wherein a gate of the first transistor and a gate of the fourth transistor are electrically connected to a first terminal,

wherein a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to a second terminal,

wherein the second terminal is electrically connected between the second transistor and the third transistor,

wherein a gate of the second transistor and a gate of the third transistor are electrically connected to a third terminal,

wherein the third terminal is electrically connected between the fifth transistor and the sixth transistor,

wherein each of the second transistor and the fifth transistor is a p-channel transistor, and

wherein each of the first transistor, the third transistor, the fourth transistor, and the sixth transistor is a transistor comprising an oxide semiconductor layer.

11. The semiconductor device according to claim 10 further comprising:

a second memory having a structure similar to that of the first memory;

a seventh transistor; and

a eighth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the third terminal of the first memory, and

wherein one of a source and a drain of the eighth transistor is electrically connected to the second terminal of the first memory and the third terminal of the second memory.

12. The semiconductor device according to claim 11,

wherein a gate of the seventh transistor is electrically connected to a line to which a clock signal is input,

wherein a gate of the eighth transistor is electrically connected to a line to which an inversion signal of the clock signal is input, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to a data input signal line.