MEMORY SYSTEM

• US 20120268994A1
• Filed: 05/02/2012
• Published: 10/25/2012
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NAGASHIMA, Hiroyuki
• Granted Patent: US 8,929,140 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Claims

1. A memory system comprising:

a nonvolatile semiconductor memory device including

a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell; and

a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,

wherein the control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

2. The memory system according to claim 1, wherein the control unit changes the read level based on at least one of a write count, an erase count, and a read count of the nonvolatile semiconductor memory device.

3. The memory system according to claim 2, wherein the control unit reads data from the memory cell once using one of a read level higher than an original read level to be used to read a threshold voltage set in the memory cell and a read level lower than the original read level.

4. The memory system according to claim 2, wherein the control unit reads data from the memory cell using both a read level higher than an original read level to be used to read a threshold voltage set in the memory cell and a read level lower than the original read level.

5. The memory system according to claim 2, wherein the control unit has a management area to record a standing time of the nonvolatile semiconductor memory device, and when the standing time recorded in the management area is not less than a predetermined time, reads data from the memory cell using a read level lower than an original read level to be used to read a threshold voltage set in the memory cell.

6. The memory system according to claim 2, wherein the control unit includes a management unit configured to manage a write count, an erase count, a read count, and a voltage application count upon write and erase for each of the plurality of blocks of the nonvolatile semiconductor memory device, and changes the read level of the memory cell based on data managed by the management unit.

7. The memory system according to claim 1, wherein the control unit executes monitor read for each block using a plurality of different read levels upon activating the system or at a predetermined timing, records a read level for a smallest error bit count in a management area as status data, and upon data read, sets the read level based on the status data recorded in the management area.

19. The memory system according to claim 1, wherein the control unit performs a read-operation using the original read level of the memory cell, a read operation using the read level shifted to be higher than the original read level, and a read operation using the read level shifted to be lower than the original read level, and if the number of errors proves to be large as the result of determination of the error detection unit, performs a refresh operation.

8. A memory system comprising:

a nonvolatile semiconductor memory device including

a memory cell array having a plurality of blocks each including a plurality of memory cells, and

a voltage generation unit configured to change a read level of the memory cell; and

a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,

wherein the control unit includes an error detection unit configured to detect an error from read data, and

performs retry read to repeat read again when the error detection unit has detected an error.

9. The memory system according to claim 8, wherein the control unit performs the retry read using a read level shifted to be higher than an original read level of the memory cell and a read level lower than the original read level.

10. The memory system according to claim 8, wherein the control unit performs the retry read while changing a read time.

11. The memory system according to claim 10, wherein the control unit changes the read time by one of changing a precharge voltage of a sense node of the memory cell and changing the number of times of sense upon read.

12. The memory system according to claim 10, wherein the control unit performs the retry read while setting a read voltage of an unselected word line adjacent to a selected word line to be higher than an original read voltage.

14. The memory system according to claim 12, wherein upon read, the control unit sets the read level based on the data recorded in the management area.

13. A memory system comprising:

a nonvolatile semiconductor memory device including

a memory cell array having a plurality of blocks each including a plurality of memory cells, and

a voltage generation unit configured to change a read level of the memory cell; and

a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,

wherein the control unit includes an error detection unit configured to detect an error from read data, and

a management area configured to record management data, and

when the error detection unit has detected an error, the control unit performs retry read using a read level shifted to be higher than an original read level of the memory cell and a read level lower than the original read level, and records, in the management area, data of a read level corresponding to a satisfactory result of the retry read.

15. A memory system comprising:

a nonvolatile semiconductor memory device including

a memory cell array having a plurality of blocks each including a plurality of memory cells, and

a voltage generation unit configured to change a read level of the memory cell; and

a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,

wherein the control unit includes an error detection unit configured to detect an error from read data, and

when the error detection unit has detected an error, the control unit performs a read operation using a read level shifted to be higher than an original read level of the memory cell, and if the number of errors proves to be small as a result of determination of the error detection unit, performs the next read operation using the read level shifted to be higher.

16. The memory system according to claim 15, wherein the control unit performs the read operation using the read level shifted to be higher than the original read level of the memory cell, and if the number of errors proves to be large as the result of determination of the error detection unit, performs the read operation using a read level shifted to be lower than the original read level of the memory cell.

17. The memory system according to claim 16, wherein when the read operation is performed using the read level shifted to be lower than the original read level of the memory cell, the control unit performs a refresh operation.

18. The memory system according to claim 15, wherein the control unit performs the read operation using the read level shifted to be higher than the original read level of the memory cell, and if the number of errors proves to be large as the result of determination of the error detection unit, performs the read operation using the original read level of the memory cell, and if the number of errors proves to be large as the result of determination of the error detection unit, performs a refresh operation.