RELIABLE DIVERSITY ARCHITECTURE FOR A MOBILE DTV SYSTEM

• US 20120269277A1
• Filed: 12/03/2009
• Published: 10/25/2012
• Est. Priority Date: 12/03/2009
• Status: Active Grant

• Current Assignee: Magnolia Licensing LLC (IP Edge LLC)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Markman, Ivonete, Bouillet, Aaron Reel, LoPresto, Scott Matthew
• Granted Patent: US 9,397,772 B2
• Time in Patent Office: Days
• US Class Current: 375/240.27
• CPC Class Codes: H04H 40/18 Arrangements characterised by circuits or components specially adapted for receiving
• CPC Class Codes: H04H 60/11 Arrangements for counter-measures when a portion of broadcast information is unavailable
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

A digital data stream comprises alternating groups of information blocks and groups of parity blocks, each group of information blocks includes multiple information blocks and each group of parity blocks includes multiple parity blocks. An apparatus for receiving a digital data stream comprises a demodulator that receives and demodulates a digital data stream. An equalizer compensates for distortions in the digital data stream. A delay buffer generates a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing a delayed version of the compensated digital data stream. A forward error correction block receives and processes the first and second streams of digital data from the delay buffer, and outputs an error corrected stream of digital data. A transport block receives and processes the error corrected stream from the forward error correction block for display

Claims

1. An apparatus for receiving a digital data stream, the digital data stream comprising alternating groups of information blocks and groups of parity blocks, each group of information blocks including a plurality of information blocks and each group of parity blocks including a plurality of parity blocks, the apparatus comprising:

a demodulator that receives the digital data stream and demodulates the digital data stream;

an equalizer, that compensates for distortions in the digital data stream to generate a compensated digital data stream;

a delay buffer, that generates a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing the compensated digital data stream delayed for a predetermined period;

a forward error correction block, that receives and processes the first and second streams of digital data from the delay buffer, and outputs an error corrected stream of digital data; and

a transport block, that receives and processes the error corrected stream from the forward error correction block for display.

2. The apparatus of claim 1, wherein the forward error correction block comprises a plurality of forward error correction cores, a first core of the plurality of forward error correction cores comprising:

a first subcore, that processes the first stream of digital data;

a second subcore, that processes the second stream of digital data;

a stagger multiplexer, that generates a combined stream of digital data from the first and second processed streams of digital data; and

a stagger demultiplexer, that processes the combined stream of digital data to generate two streams of extrinsic digital data;

wherein the first subcore further processes one stream of extrinsic digital data to output a third digital data stream, the second subcore further processes the other stream of extrinsic digital data to output a fourth digital data stream, and the first and third streams are provided to a first subcore of a subsequent forward error correction core of the plurality of forward error correction cores and the second and fourth streams are provided to a second subcore of the subsequent forward error correction core.

3. The apparatus of claim 2, wherein the stagger multiplexer generates a first intermediate stream by extracting groups of parity blocks from the first stream of digital data and inserting a zero block in place of each group of parity blocks and generates a second intermediate stream by extracting groups of information blocks from the second stream of digital data and inserting a zero block in place of each group of information blocks;

wherein the combined stream of digital data is generated by alternately extracting an individual information block from the first intermediate stream of digital data and an individual parity block from the second intermediate stream of digital data.

4. The apparatus of claim 2, wherein the stagger demultiplexer generates the one stream of extrinsic digital data by extracting individual information blocks from the combined stream of digital data to form groups of information blocks with zero blocks between each group of information blocks and generates the other stream of extrinsic digital data by extracting individual parity blocks from the combined stream of digital data to form groups of parity blocks with zero blocks between each group of parity blocks.

5. The apparatus of claim 2, wherein each of the plurality of forward error correction cores comprises:

a first subcore, that processes the first and third streams of digital data;

a second subcore, that processes the second and fourth streams of digital data;

a stagger multiplexer, that generates a combined stream of digital data from the first and second processed streams of digital data; and

a stagger demultiplexer, that processes the combined stream of digital data to generate two streams of extrinsic digital data;

wherein the first subcore further processes one stream of extrinsic digital data to output a third digital data stream, the second subcore further processes the other stream of extrinsic digital data to output a fourth digital data stream, and the first and third streams are provided to a first subcore of a subsequent forward error correction core of the plurality of forward error correction cores and the second and fourth streams are provided to a second subcore of the subsequent forward error correction core.

6. The apparatus of claim 2, wherein the forward error correction block comprises a last core comprising:

a first subcore, that processes the first and third streams of digital data;

a second subcore, that processes the second and fourth streams of digital data;

a stagger multiplexer, that generates a combined stream of digital data from the first and second processed streams of digital data; and

a decoding block, that processes the combined stream of digital data and outputs the combined stream of digital data as the error corrected stream of digital data.

7. The apparatus of claim 5, wherein the forward error correction block comprises a last core comprising:

a first subcore, that processes the first and third streams of digital data;

a second subcore, that processes the second and fourth streams of digital data;

a stagger multiplexer, that generates a combined stream of digital data from the first and second processed streams of digital data; and

a decoding block, that processes the combined stream of digital data and outputs the combined stream of digital data as the error corrected stream of digital data.

8. The apparatus of claim 2, wherein the forward error correction block further comprises a forward error correction core that processes the first and second streams of digital data to generate a reencoded data stream, the reencoded data stream being provided to the equalizer.

9. An apparatus for decoding a digital data stream, comprising:

a first subcore, that processes a first stream of digital data producing a first processed stream of digital data;

a second subcore, that processes a second stream of digital data producing a second processed stream of digital data;

a stagger multiplexer, that generates a combined stream of digital data from the first and second processed streams of digital data; and

a stagger demultiplexer, that processes the combined stream of digital data to generate a first stream and a second stream of extrinsic digital data;

wherein the first subcore further processes the first stream of extrinsic digital data to output a third digital data stream, the second subcore further processes the second stream of extrinsic digital data to output a fourth digital data stream, and the first and third streams are provided to a first subcore of a subsequent forward error correction core of the plurality of forward error correction cores and the second and fourth streams are provided to a second subcore of the subsequent forward error correction core.

10. The apparatus of claim 9, wherein the stagger multiplexer generates a first intermediate stream by extracting groups of parity blocks from the first stream of digital data and inserting a zero block in place of each group of parity blocks and generates a second intermediate stream by extracting groups of information blocks from the second stream of digital data and inserting a zero block in place of each group of information blocks;

wherein the combined stream of digital data is generated by alternately extracting an individual information block from the first intermediate stream of digital data and an individual parity block from the second intermediate stream of digital data.

11. The apparatus of claim 9, wherein the stagger demultiplexer generates the one stream of extrinsic digital data by extracting individual information blocks from the combined stream of digital data to form groups of information blocks with zero blocks between each group of information blocks and generates the other stream of extrinsic digital data by extracting individual parity blocks from the combined stream of digital data to form groups of parity blocks with zero blocks between each group of parity blocks.

12. A method for receiving a digital data stream, the digital data stream comprising alternating groups of information blocks and groups of parity blocks, each group of information blocks including a plurality of information blocks and each group of parity blocks including a plurality of parity blocks, the method comprising:

demodulating, in a demodulator, the digital data stream producing a demodulated digital data stream;

compensating, with an equalizer, the demodulated digital data stream for distortions producing a compensated digital data stream;

generating, with a delay buffer, a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing the compensated digital data stream delayed for a predetermined delay period;

processing, with a forward error correction block, the first and second streams of digital data to generate an error corrected stream of digital data;

transmitting, the error corrected stream of digital data for display.

13. The method of claim 12, wherein the step of processing comprises processing the first and second streams of digital data with a plurality of forward error correction cores.

14. The method of claim 13, wherein the processing comprises:

processing, the first and second streams of digital data;

generating, in a stagger multiplexer, a combined stream of digital data from the first and second processed streams;

generating, in a stagger demultiplexer, a first stream and a second stream of extrinsic digital data from the combined stream of digital data;

processing, in the first subcore, the first stream of extrinsic digital data to output a third digital data stream;

processing, in the second subcore, the second stream of extrinsic digital data to output a fourth digital data stream;

outputting the first and third streams of digital data to a first subcore of one of a plurality of forward error correction cores; and

outputting the second and fourth streams of digital data to a second subcore of the one of the plurality of forward error correction cores.

15. The method of claim 14, wherein generating, in a stagger multiplexer, comprises:

extracting groups of parity blocks from the first stream of digital data and inserting a zero block in place of each group of parity blocks to form a first intermediate stream of digital data;

extracting groups of information blocks from the second stream of digital data and inserting a zero block in place of each group of information blocks to form a second intermediate stream of digital data;

alternately extracting an individual information block from the first intermediate stream of digital data and an individual parity block from the second intermediate stream of digital data producing extracted individual blocks; and

combining the extracted individual blocks to form the combined stream of digital data.

16. The method of claim 14, wherein the step of generating, in a stagger demultiplexer, comprises:

extracting individual information blocks from the combined stream of digital data to form groups of information blocks and placing zero blocks between each group of information blocks to generate one stream of extrinsic data;

extracting individual parity blocks from the combined stream of digital data to form groups of parity blocks and placing zero blocks between each group of parity blocks to generate the second stream of extrinsic data.