DOUBLE PRECISION APPROXIMATION OF A SINGLE PRECISION OPERATION
First Claim
1. A method for double precision approximation of a single precision operation, comprising the steps of:
- (A) storing an input value in a processor, wherein (i) said processor implements a plurality of first operations in hardware, (ii) each of said first operations receives a first variable as an argument, (iii) said first variable is implemented in a fixed point format at a single precision and (iv) said input value is implemented in said fixed point format at a double precision; and
(B) generating an output value by emulating a selected one of said first operations using said input variable as said argument, wherein (i) said emulation utilizes said selected first operation in said hardware, (ii) said output value is implemented in said fixed point format at said double precision and (iii) said emulation is performed by a plurality of instructions executed by said processor.
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Abstract
A method for double precision approximation of a single precision operation is disclosed. The method may include steps (A) to (B). Step (A) may store an input value in a processor. The processor generally implements a plurality of first operations in hardware. Each first operation may receive a first variable as an argument. The first variable may be implemented in a fixed point format at a single precision. The input value may be implemented in the fixed point format at a double precision. Step (B) may generate an output value by emulating a selected one of the first operations using the input value as the argument. The emulation may utilize the selected first operation in hardware. The output value may be implemented in the fixed point format at the double precision. The emulation is generally performed by a plurality of instructions executed by the processor.
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Citations
20 Claims
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1. A method for double precision approximation of a single precision operation, comprising the steps of:
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(A) storing an input value in a processor, wherein (i) said processor implements a plurality of first operations in hardware, (ii) each of said first operations receives a first variable as an argument, (iii) said first variable is implemented in a fixed point format at a single precision and (iv) said input value is implemented in said fixed point format at a double precision; and (B) generating an output value by emulating a selected one of said first operations using said input variable as said argument, wherein (i) said emulation utilizes said selected first operation in said hardware, (ii) said output value is implemented in said fixed point format at said double precision and (iii) said emulation is performed by a plurality of instructions executed by said processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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a processor configured to store an input value, wherein (i) said processor implements a plurality of first operations in hardware, (ii) each of said first operations receives a first variable as an argument, (iii) said first variable is implemented in a fixed point format at a single precision and (iv) said input value is implemented in said fixed point format at a double precision; and a memory containing a plurality of processor executable instructions, said instructions being configured to generate an output value by emulating a selected one of said first operations using said input variable as said argument, wherein (i) said emulation utilizes said selected first operation in said hardware and (ii) said output value is implemented in said fixed point format at said double precision. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. An apparatus comprising:
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means for processing configured to store an input value, wherein (i) said means for processing implements a plurality of first operations in hardware, (ii) each of said first operations receives a first variable as an argument, (iii) said first variable is implemented in a fixed point format at a single precision and (iv) said input value is implemented in said fixed point format at a double precision; and means for storing a plurality of processor executable instructions, said instructions being configured to generate an output value by emulating a selected one of said first operations using said input value as said argument, wherein (i) said emulation utilizes said selected first operation in said hardware and (ii) said output value is implemented in said fixed point format at said double precision.
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Specification