SEMICONDUCTOR MEMORY SYSTEM SELECTIVELY STORING DATA IN NON-VOLATILE MEMORIES BASED ON DATA CHARACTERSTICS

• US 20120271985A1
• Filed: 04/20/2012
• Published: 10/25/2012
• Est. Priority Date: 04/20/2011
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Young-joon, Jeong, Hyo-jin, Ju, Jae-hyeon
• Application Number:
  US13/452,529
• Publication Number:
  US 20120271985A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A semiconductor memory device includes a memory block and memory transmission and reception unit. The memory block includes a first non-volatile memory allocated to a first region having a first address range of physical addresses and a second non-volatile memory allocated to a second region having a second address range different from the first address range, which are mapped to logical addresses of a storing region in a host device. The memory transmission and reception unit performs data input and output operations between the host device and the first non-volatile memory using a first data input and output type, and performs data input and output operations between the host device and the second non-volatile memory using a second data input and output type. The first data input and output type performs the data input and output operations by access units corresponding to the first non-volatile memory.

Claims

1. A semiconductor memory system comprising:

a memory controller; and

a semiconductor memory device, comprising;

a memory block including a first non-volatile memory allocated to a first region having a first address range of physical addresses and a second non-volatile memory allocated to a second region having a second address range of physical addresses different from the first address range, the first and second address ranges being mapped to logical addresses of a storing region in a host device; and

a memory transmission and reception unit for performing data input and output operations between the host device and the first non-volatile memory using a first data input and output type, and performing data input and output operations between the host device and the second non-volatile memory using a second data input and output type,

wherein data to be stored in the memory device are selectively stored via the memory transmission and reception unit in one of the first non-volatile memory or the second non-volatile memory based on characteristics of the data.

2. The semiconductor memory system of claim 1, wherein the first data input and output type performs the data input and output operations between the host device and the first non-volatile memory by access units corresponding to the first non-volatile memory.

3. The semiconductor memory system of claim 2, wherein the first data input and output type includes an execute-in-place (XIP) method.

4. The semiconductor memory system of claim 3, wherein the second data input and output type includes a block device input and output type.

5. The semiconductor memory system of claim 1, wherein a data transmission unit of the first data input and output type is different from a data transmission unit of the second data input and output type.

6. The semiconductor memory system of claim 1, wherein the first non-volatile memory includes at least one of phase-change random access memory (PRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), and ferroelectric random access memory (FRAM).

7. The semiconductor memory system of claim 1, wherein the first non-volatile memory stores data smaller in size and is more frequently accessed than the data stored in the second non-volatile memory.

8. The semiconductor memory system of claim 7, wherein the first non-volatile memory stores boot data used in the processor.

9. The semiconductor memory system of claim 7, wherein the first non-volatile memory stores system code used in the host device or application code executed in the host device.

10. The semiconductor memory system of claim 1, wherein the first non-volatile memory is used as a virtual memory of the host device.

11. The semiconductor memory system of claim 7, wherein the first non-volatile memory stores meta data of a file system used in the host device.

12. The semiconductor memory system of claim 1, wherein the second non-volatile memory includes a NAND flash memory.

13. The semiconductor memory system of claim 12, wherein the second non-volatile memory operates as at least one of a single-level cell flash memory and a multi-level cell flash memory.

14. The semiconductor memory system of claim 12, wherein the second non-volatile memory stores user data generated by a user.

15. The semiconductor memory system of claim 12, wherein the first non-volatile memory stores meta data mapping virtual addresses used in the processor to physical addresses of the second non-volatile memory.

16. A semiconductor memory device comprising:

a memory block including a first non-volatile memory allocated to a first region defined by a first address range within a range of physical addresses mapped to logical addresses of a storing region provided in an external processor, and a second non-volatile memory allocated in a second region defined by a second address range within the range of physical addresses, the second region being different from the first region; and

a memory transmission and reception unit for performing data input and output operations between the external processor and the first non-volatile memory using a first data input and output type, and for performing data input and output operations between the external processor and the second non-volatile memory using a second data input and output type,

wherein the first data input and output type comprises performing the data input and output operations between the processor and the first non-volatile memory by an access unit for the first non-volatile memory.

17. The semiconductor memory device of claim 16, wherein the second data input and output type comprises performing the data input and output operations between the processor and the second non-volatile memory by an access unit for the second non-volatile memory, which is different from the access unit for the first non-volatile memory.

18. The semiconductor memory device of claim 16, wherein a start address of the second address range is an address next to a finish address of the first address range.

19. A semiconductor memory device comprising:

a memory block including a first non-volatile memory configured to store data having first data characteristics and a second non-volatile memory configured to store data having second data characteristics different from the first data characteristics, the first and second non-volatile memories having difference ranges of physical addresses; and

a memory transmission and reception unit comprising a first transmission and reception unit configured for exchanging the data having the first data characteristics between a host device and the first non-volatile memory using a first data input and output type, and a second transmission and reception unit configured for exchanging the data having the second data characteristics between the host device and the second non-volatile memory using a second data input and output type, wherein the first data input output type comprises a direct access method.

20. The semiconductor memory device of claim 19, wherein the first non-volatile memory comprises one of phase-change random access memory (PRAM), resistive random-access memory (RRAM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), and

wherein the second non-volatile memory comprises a flash memory.