CACHE MEMORY WITH DYNAMIC LOCKSTEP SUPPORT

• US 20120272007A1
• Filed: 04/19/2011
• Published: 10/25/2012
• Est. Priority Date: 04/19/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C.
• Granted Patent: US 9,086,977 B2
• Time in Patent Office: Days
• US Class Current: 711/128
• CPC Class Codes: G06F 11/1629 Error detection by comparing the output of redundant processing systems
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2201/845 Systems in which the redundancy can be transformed in increased performance
• CPC Class Codes: G06F 2212/1016 Performance improvement

Abstract

Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution mode(s). For example, in embodiments that employ cache storage organized as a set associative cache, partition may be achieved by reserving a subset of the ways in the cache for use when operating in lockstep mode. Some or all of the remaining ways are available for use when operating in non-lockstep execution mode(s). In some embodiments, a subset of the cache sets, rather than cache ways, may be reserved in a like manner, though for concreteness, much of the description that follows emphasizes way-partitioned embodiments.

Claims

1. A method of operating a computational system that includes a plurality of processors each having an associated cache partitioned into lockstep and non-lockstep partitions, the method comprising:

dynamically transitioning between a lockstep mode of operation and a non-lockstep mode of operation, wherein in the lockstep mode of operation, the plural processors each execute a same code sequence in temporal correspondence, and wherein in the non-lockstep mode of operation, the plural processors are capable of executing differing code sequences;

in the non-lockstep mode, satisfying at least some load hits from the lockstep partition and at least some other load hits from the non-lockstep partition; and

in the lockstep mode, satisfying load hits only from the lockstep partition.

2. The method of claim 1, further comprising:

during operation of the computational system, partitioning the associated caches into lockstep and non-lockstep partitions.

3. The method of claim 1, further comprising:

for a lockstep mode hit in the non-lockstep partition, invalidating the hit entry in the non-lockstep partition.

4. The method of claim 3,

wherein for a lockstep mode load hit in the non-lockstep partition, the invalidating is contemporaneous with access request and triggers allocation and fill of a corresponding entry in the lockstep partition.

5. The method of claim 3,

wherein for a lockstep mode store hit in the non-lockstep partition, the invalidating is contemporaneous with access request and triggers allocation and fill of a corresponding entry in the lockstep partition.

6. The method of claim 3, further comprising:

for a non-lockstep mode store hit in the lockstep partition, invalidating the hit entry in the lockstep partition.

7. The method of claim 6,

wherein for non-lockstep mode store hits in the lockstep partition, the invalidating is performed in accord with a programmable selection of invalidation behavior.

8. The method of claim 6,

wherein for a non-lockstep mode store hit in the lockstep partition, the invalidating is contemporaneous with access request and triggers a snoop invalidation of a corresponding entry in another cache.

9. The method of claim 6,

wherein for a non-lockstep mode store hit in the lockstep partition, the store completes in the lockstep partition but is subsequently invalidated contemporaneous with transition from the non-lockstep mode to the lockstep mode.

10. The method of claim 1,

in the non-lockstep mode, freezing allocations to the lockstep partition;

and

in the lockstep mode, freezing allocations to the non-lockstep partition.

11. The method of claim 1, wherein the partitioning is by cache ways, and further comprising:

reserving a programmable number of the cache ways as the lockstep partition.

12. The method of claim 1,

wherein the partitioning is by cache sets.

13. The method of claim 1,

wherein, in the lockstep mode of operation, the temporal correspondence provides execution, on each of the plural processors, of same respective instructions of the same code sequence in execution cycles that are either identical or exhibit a generally fixed phase relationship.

14. An apparatus comprising:

plural processors dynamically transitionable between lockstep and non-lockstep modes of operation, wherein in the lockstep mode of operation, the plural processors each execute a same code sequence in temporal correspondence, and wherein in the non-lockstep mode of operation, the plural processors are capable of executing differing code sequences; and

respective caches coupled to, and associated with, respective ones of the plural processors, the respective caches each including control logic operable to, in the non-lockstep mode, satisfy at least some load hits from a lockstep partition thereof and at least some other load hits from a non-lockstep partition thereof, and to, in the lockstep mode, satisfy load hits only from the lockstep partition but, for a hit in the non-lockstep partition, invalidate the hit entry in the non-lockstep partition.

15. The apparatus of claim 14,

wherein the control logic is further operable to, in the lockstep mode, freeze allocations to entries of the non-lockstep partition and, in the non-lockstep mode, freeze allocations to entries of the lockstep partition.

16. The apparatus of claim 14, further comprising:

a control register coupled to the control logic, the control register defining a changeable boundary between the lockstep and non-lockstep partition portions of the caches.

17. The apparatus of claim 14, further comprising:

a control register coupled to the control logic, the control register defining a selectable invalidation behavior for non-lockstep mode, write hits in the lockstep partition.

18. The apparatus of claim 14,

wherein partition of the respective caches into the lockstep and non-lockstep partitions is by cache ways.

19. The apparatus of claim 18,

wherein partition of the respective caches into the lockstep and non-lockstep partitions is by cache sets.

20. An integrated circuit comprising:

a processor capable of dynamic transitions between lockstep and non-lockstep modes of operation;

a cache associated with the processor and having control logic operable to define a changeable boundary between a lockstep partition and non-lockstep partition of the cache; and

control logic responsive to a current mode indication and operable to, in the lockstep mode, freeze allocations to entries of the non-lockstep partition and, in the non-lockstep mode, freeze allocations to entries of the lockstep partition.

21. The apparatus of claim 20, further comprising:

a control register coupled to the control logic, the control register to define a selectable invalidation behavior for non-lockstep mode, write hits in the lockstep partition.